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features _?q?? ? =olj=nck cost-effective single-ch ip solution for stereo headset and wireless speaker applications a2dp1.2 and avrcp1.0 profiles enabled with sbc encoder for streaming audio over bluetooth and for remote control functionality mp3 decoder for improved audio quality and reduced power consumption (mp3 decode functionality requires an appropriate licence from thomson, see section 17.1) configurable a2dp 5-band eq high-quality audio 95db snr on dac playback 64mips kalimba dsp coprocessor faststream, csrs low-la tency codec for video and gaming applications hfp 1.5 (includes 3-way calling) and hsp 1.0 support cvc support for echo and noise reduction low-power consumption: over 10 hours of audio playback from a 180mah battery fully qualified bluetooth v2.1 + edr specification system with support for secure simple pairing best-in-class bluetooth radio with 8dbm transmit power and -92dbm receive sensitivity 2 integrated linear regulators with 1.5v output from 1.7v to 1.95v input integrated switch-mode regulator integrated lithium battery charger 68-lead 8 x 8 x 0.9mm, 0.4mm pitch qfn package green (rohs compliant and no antimony or halogenated flame retardants) bluetunes rom stereo headset solution development kit available, includes example design. order code btn-003-1a _?q??=olj=p ?=e~??=p???? single-chip bluetooth ? v2.1 + edr system production information bc57f687a05 issue 3 general description based on _?`? ? rjj???~=olj=nck , the _?q??=olj=nck integrates a bluetooth radio, baseband, dsp, high-quality audio codec, smps, ldo and a battery charger for minimal bom, component count and pcb area. bluetunes rom qfn uses advanced dsp features for the latest stereo enhancements and to improve audio quality, including sbc and mp3 decoder, support for faststream (low-latency codec) and 5?band eq. 2.4 ghz radio i/o rf in rf out ram mcu kalimba dsp rom eeprom uart pio spi i 2 c audio in/out xtal applications stereo headset solution with support for echo and noise reduction wireless stereo speakers bluetunes rom qfn include s as standard cvc dual and single microphone algorithms for echo and noise suppression. cvc dual-microphone algorithm can provide >30db of noise suppression in both stationary and dynamic noise conditions such as; babble, road, music and competing voices. in addition an acoustic echo canceller is now integrated into the cvc dual- microphone solution, further enhancing the far-end user experience. a cvc single-microphone provides full-duplex echo cancellation and a 10db stationary noise suppressor. bluetunes rom qfn includes secure simple pairing, which greatly simplifies the pairing process, making it even easier to use a bluetooth headset. cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 1 of 74 _?q??=olj=nck data sheet free datasheet http:///
document history revision date change reason 1 23 oct 08 original publication of this document. 2 25 feb 09 production information. 3 22 mar 10 status information, ordering inf ormation and adc digital gain u pdates. modification to electri cal characteristics structure and variou s editorial changes. if you have any comments about this document, email comments@csr.com giving the number, title and section with your feedback. document history cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 2 of 74 _?q??=olj=nck data sheet free datasheet http:///
status information the status of this data sheet is production information . csr product data sheets progress according to the following for mat: advance information information for designers concerning csr product in development . all values specified are the target values of the design. minimum and maximum values specified are only given as guidance to the final specification limits and must not be considered as the final values. all detailed specifications including pinouts and electrical sp ecifications may be changed by csr without notice. pre-production information pinout and mechanical dimension specifications finalised. all v alues specified are the target values of the design. minimum and maximum values specified are only given as guidance to the final specification limits and must not be considered as the final values. all electrical specifications may be changed by csr without not ice. production information final data sheet including the guaranteed minimum and maximum l imits for the electrical specifications. production data sheets supersede all previous document versions . life support policy and use i n safety-critica l applications csr's products are not authorised for use in life-support or sa fety-critical applic ations. use in such applications is done at the sole di scretion of the custome r. csr wil l not warra nt the use of its devices in such applications. csr green semiconductor products and rohs compliance bluetunes rom qfn devices meet the requirements of directive 20 02/95/ec of the european parliament and of the council on the restriction of hazardous substance (rohs). bluetunes rom qfn devices are also free from halogenated or ant imony trioxide-based flam e retardants and other hazardous chemicals. for more information, see csr's environmental co mpliance statement for csr green semiconductor products . trademarks, patent s and licences unless otherwise stated, words and logos marked with ? or ? are trademarks registered or owned by csr plc or its affiliates. bluetooth ? and the bluetooth ? logos are trademarks owned by bluetooth ? sig, inc. and licensed to csr. other products, services and names used in this document m ay have been trademarked by their respective owners. the publication of this information does not imply that any lic ense is granted under any patent or other rights owned by csr plc and/or its affiliates. csr reserves the righ t to make technical changes to its product s as part of its development programme. while every care has been taken to ensure the accuracy of the c ontents of this document, csr cannot accept responsibility for any errors. refer to www.csrsupport.com for compliance and conformance to standards information. no statements or representations in this document are to be con strued as advertising, marke ting, or offering for sale in the united states imported covered products subject to the c ease and desist order issued by the u.s. international trade commission in its investigation no. 337-ta- 602. such products include sirfstariii chips that operate with sirf software that supports sirfinstantfix, and/or sirfloc servers, or contains syncfreenav functionality. status information cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 3 of 74 _?q??=olj=nck data sheet free datasheet http:///
contents 1 device details ............................................... ............................................................... ................................... 8 2 functional block diagram ..................................... ............................................................... ........................... 9 3 package information .......................................... ............................................................... ............................ 10 3.1 pinout diagram ............................................. ............................................................... ........................ 10 3.2 device terminal fun ctions .................................. ............................................................... ................. 11 3.3 package dimension s ......................................... ............................................................... ................... 15 3.4 pcb design and assembly c onsiderations ..................... ............................................................... ..... 16 3.5 typical solder reflow profile .............................. ............................................................... .................. 16 4 bluetooth modem .............................................. ............................................................... ............................. 17 4.1 rf ports ................................................... ............................................................... ............................. 17 4.1.1 rf_n and rf_p ............................................ ............................................................... .......... 17 4.2 rf receiver ................................................ ............................................................... .......................... 17 4.2.1 low noise ampli fier ...................................... ............................................................... .......... 17 4.2.2 rssi analogue to digita l converter ....................... ............................................................... . 17 4.3 rf transmitter ............................................. ............................................................... ......................... 18 4.3.1 iq modulator ............................................. ............................................................... .............. 18 4.3.2 power amplifier .......................................... ............................................................... ............. 18 4.4 bluetooth rad io synthesiser ................................ ............................................................... ................ 18 4.5 baseband ................................................... ............................................................... ........................... 18 4.5.1 burst mode control ler .................................... ............................................................... ......... 18 4.5.2 physical layer hardware engine ........................... ............................................................... . 18 4.6 basic rate modem ........................................... ............................................................... .................... 18 4.7 enhanced data rate modem ................................... ............................................................... ............ 18 5 clock generation ............................................. ............................................................... .............................. 20 5.1 clock architecture ......................................... ............................................................... ........................ 20 5.2 input frequencies and ps key settings ...................... ............................................................... ......... 20 5.3 external reference cl ock ................................... ............................................................... .................. 20 5.3.1 input: xtal_in ........................................... ............................................................... ............. 20 5.3.2 xtal_in impedance in external mode ....................... ........................................................... 21 5.3.3 clock start-up delay ..................................... ............................................................... .......... 21 5.3.4 clock timing accuracy .................................... ............................................................... ........ 21 5.4 crystal oscillator: xtal_in and xtal_out ................... ............................................................... ..... 22 5.4.1 load capacitance ......................................... ............................................................... .......... 23 5.4.2 frequency trim ........................................... ............................................................... ............ 23 5.4.3 transconductance driver model ............................ ............................................................... . 24 5.4.4 negative resistance model ................................ ............................................................... .... 24 5.4.5 crystal ps key settings .................................. ............................................................... ........ 25 6 bluetooth stack microcontroller .............................. ............................................................... ....................... 26 6.1 programmable i/o ports, pio and aio ........................ ............................................................... ......... 26 7 kalimba dsp .................................................. ............................................................... ............................... 27 8 memory interface and m anagement .............................. ............................................................... ................ 28 8.1 memory management unit ..................................... ............................................................... .............. 28 8.2 system ram ................................................. ............................................................... ........................ 28 8.3 kalimba dsp ram ............................................ ............................................................... ................... 28 8.4 internal rom ............................................... ............................................................... ......................... 28 9 serial interfaces ............................................ ............................................................... ................................. 29 9.1 uart interface ............................................. ............................................................... ........................ 29 9.1.1 uart configuration wh ile reset is active ................. ........................................................... 31 9.2 programming and debug interface ............................ ............................................................... ........... 31 9.2.1 instruction cycle ........................................ ............................................................... .............. 31 contents cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 4 of 74 _?q??=olj=nck data sheet free datasheet http:///
9.2.2 multi-slave operat ion .................................... ............................................................... .......... 31 9.3 i 2 c interface ................................................... ............................................................... ....................... 31 10 audio interface ............................................. ............................................................... .................................. 33 10.1 audio input and output .................................... ............................................................... ..................... 33 10.2 audio codec interface ..................................... ............................................................... ..................... 33 10.2.1 audio codec block diagram ............................... ............................................................... .... 34 10.2.2 adc ..................................................... ............................................................... .................... 34 10.2.3 adc sample rate ......................................... ............................................................... .......... 34 10.2.4 adc digital gain ........................................ ............................................................... ............. 34 10.2.5 adc analogue gain ....................................... ............................................................... ......... 35 10.2.6 dac ..................................................... ............................................................... .................... 35 10.2.7 dac sample rate selection ............................... ............................................................... .... 36 10.2.8 dac digital gain ........................................ ............................................................... ............. 36 10.2.9 dac analogue gain ....................................... ............................................................... ......... 36 10.2.10 microphone input ....................................... ............................................................... ............. 37 10.2.11 line input ............................................. ............................................................... ................... 39 10.2.12 output stage ........................................... ............................................................... ................ 40 10.2.13 mono opera tion ......................................... ............................................................... ............. 40 10.2.14 side tone .............................................. ............................................................... .................. 40 10.2.15 integrated digital filter .............................. ............................................................... .............. 41 10.3 auristream codec .......................................... ............................................................... ...................... 42 11 power control and regulation ................................ ............................................................... ....................... 43 11.1 power sequenc ing .......................................... ............................................................... ...................... 43 11.2 external voltage source ................................... ............................................................... .................... 43 11.3 low-voltage linear reg ulator .............................. ............................................................... ................. 44 11.4 low-voltage audio linear regulator ........................ ............................................................... ............. 44 11.5 switch-mode regulator ..................................... ............................................................... ................... 44 11.6 battery charger ........................................... ............................................................... ......................... 45 11.7 voltage regulator enabl e pins ............................. ............................................................... ................ 45 11.8 reset, rst# ............................................... ............................................................... .......................... 45 11.8.1 digital pin states on reset ............................. ............................................................... ........ 46 11.8.2 status after reset ...................................... ............................................................... ............. 46 11.9 led drivers ............................................... ............................................................... ........................... 46 12 example applicat ion schematic ............................... ............................................................... ..................... 48 13 electrical characteristics .................................. ............................................................... ............................. 49 13.1 absolute maximum ratings .................................. ............................................................... ................ 49 13.2 recommended oper ating conditions .......................... ............................................................... ......... 49 13.3 input/output terminal characteristics ..................... ............................................................... ............. 50 13.3.1 low-voltage linear regulator ............................ ............................................................... ..... 50 13.3.2 low-voltage linear audio regulator ...................... ............................................................... . 51 13.3.3 switch-mode regulator ................................... ............................................................... ........ 52 13.3.4 battery charger ......................................... ............................................................... .............. 53 13.3.5 reset ................................................... ............................................................... .................... 54 13.3.6 regulator enable ........................................ ............................................................... ............ 54 13.3.7 digital term inals ....................................... ............................................................... .............. 55 13.3.8 clocks .................................................. ............................................................... ................... 56 13.3.9 led driver pads ......................................... ............................................................... ............ 56 13.3.10 mono codec: a nalogue to digital converter .............. ............................................................ 57 13.3.11 stereo codec: digital to analogue converter ............ ............................................................ 58 13.3.12 auxiliary adc .......................................... ............................................................... ................ 59 13.4 esd precautions ........................................... ............................................................... ....................... 59 14 hci power consumption ....................................... ............................................................... ........................ 60 15 csr green semiconductor produ cts and rohs compliance ........ ............................................................. 6 2 contents cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 5 of 74 _?q??=olj=nck data sheet free datasheet http:///
15.1 rohs statement ............................................ ............................................................... ....................... 62 15.1.1 list of restricted materials ............................ ............................................................... .......... 62 16 bluetunes rom qfn sof tware stack ............................ ............................................................... .............. 63 16.1 stand-alone bluetunes rom qfn and kalimba dsp applications ................................................... 63 16.2 hci stack ................................................. ............................................................... ............................. 64 16.2.1 key features of the hci stack: standard bluetooth functio nality ......................................... 64 16.2.2 key features of the hci stack: extra functionality ...... ......................................................... 66 16.3 bluetunes rom stereo headset solution development kit, btn- 003-1a ........................................... 66 16.4 bluetunes rom qfn stereo headset rom software, bc57f687a05 ............................................. 66 17 ordering information ........................................ ............................................................... .............................. 68 17.1 mp3 licence statement ..................................... ............................................................... ................... 68 17.2 development kit ord ering inform ation ...................... ............................................................... ........... 68 18 tape and reel information ................................... ............................................................... ......................... 69 18.1 tape orientation .......................................... ............................................................... ......................... 69 18.2 tape dimensions ........................................... ............................................................... ....................... 69 18.3 reel information .......................................... ............................................................... ......................... 70 18.4 moisture sensitivity level ................................ ............................................................... ..................... 70 19 document references ......................................... ............................................................... .......................... 71 terms and definitions ......................................... ............................................................... .................................... 72 list of figures figure 2.1 bluetunes rom qfn functional block diagram .......... ............................................................... .... 9 figure 3.1 bluetunes rom qf n device pinout ..................... ............................................................... .......... 10 figure 3.2 bluetunes rom qfn 68 lead qfn package dimensions .... ........................................................ 15 figure 4.1 simplifi ed circuit rf_n and rf_p .................... ............................................................... ............... 17 figure 4.2 bdr and edr packet structure ........................ ............................................................... .............. 19 figure 5.1 clock architecture .................................. ............................................................... .......................... 20 figure 5.2 tcxo clock accuracy ................................. ............................................................... .................... 22 figure 5.3 crystal driver circuit .............................. ............................................................... .......................... 22 figure 5.4 crystal equivalent circuit .......................... ............................................................... ....................... 23 figure 7.1 kalimba dsp interf ace to internal functions ......... ............................................................... .......... 27 figure 9.1 universal asyn chronous receiver ..................... ............................................................... .............. 29 figure 9.2 break signal ........................................ ............................................................... ............................. 30 figure 9.3 example eeprom connection ........................... ............................................................... ............ 32 figure 10.1 bluetunes rom qfn audio interface .................. ............................................................... ........... 33 figure 10.2 codec audio input and output stages ................ ............................................................... ............. 34 figure 10.3 adc analogue amplif ier block diagram ............... ............................................................... ........... 35 figure 10.4 microphone biasing (single c hannel shown) .......... ............................................................... ........ 37 figure 10.5 differential input ( single channel shown) .......... ............................................................... ............. 39 figure 10.6 single-ended inpu t (single channel shown) .......... ............................................................... ......... 40 figure 10.7 speaker output (single channel shown) .............. ............................................................... .......... 40 figure 11.1 voltage regul ator configuration .................... ............................................................... .................. 43 figure 11.2 led equivalent circuit ............................. ............................................................... ........................ 47 figure 12.1 bluetunes rom qfn example application schematic .... .............................................................. 48 figure 16.1 stand-alone application: bluetunes rom stereo headse t solution ............................................... 63 figure 16.2 bluecore hci stack ................................. ............................................................... ........................ 64 figure 18.1 bluetunes rom qfn tape orientation ................. ............................................................... ......... 69 figure 18.2 reel dimensions .................................... ............................................................... .......................... 70 contents cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 6 of 74 _?q??=olj=nck data sheet free datasheet http:///
list of tables table 4.1 data rate schemes .................................... ............................................................... ...................... 18 table 5.1 external clock specifications ........................ ............................................................... .................... 21 table 5.2 crystal specification ................................ ............................................................... .......................... 23 table 9.1 possible uart settings ............................... ............................................................... ..................... 29 table 9.2 standard baud rates .................................. ............................................................... ...................... 30 table 9.3 instruction cycle fo r a spi transaction .............. ............................................................... ............... 31 table 10.1 adc digital gain rate selection ..................... ............................................................... .................. 35 table 10.2 dac digital gain rate selection ..................... ............................................................... .................. 36 table 10.3 dac analogue gain ra te selection .................... ............................................................... .............. 36 table 10.4 voltage ou tput steps ................................ ............................................................... ........................ 38 table 10.5 current output steps ................................ ............................................................... ........................ 39 table 11.1 bluetunes rom qfn vo ltage regulator enable pins ..... ............................................................... 45 table 11.2 bluetunes rom qfn digital pin states on reset ....... ............................................................... .... 46 list of equations equation 5.1 load capacitance .................................. ............................................................... .......................... 23 equation 5.2 trim capacitance .................................. ............................................................... ........................... 23 equation 5.3 fr equency trim .................................... ............................................................... ............................ 24 equation 5.4 pullability ....................................... ............................................................... ................................... 24 equation 5.5 transcondu ctance required for oscillation ......... ............................................................... ............ 24 equation 5.6 equivalent negative resistance .................... ............................................................... .................. 25 equation 9.1 baud rate ......................................... ............................................................... ............................... 30 equation 10.1 iir filt er transfer function, h(z) ............... ............................................................... ....................... 42 equation 10.2 iir filter plus dc blocking transfer function, h dc (z) ........................................................... ......... 42 equation 11.1 le d current ...................................... ............................................................... ............................... 47 equation 11.2 led pad voltage .................................. ............................................................... ........................... 47 contents cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 7 of 74 _?q??=olj=nck data sheet free datasheet http:///
1 device details radio common tx/rx terminal simplifies external matching; eliminates external antenna switch bist minimises production test time bluetooth v2.1 + edr specification compliant transmitter 8dbm rf transmit power with level control from on- chip 6-bit dac over a dynamic range >30db class 2 and class 3 support without the need for an external power amplifier or tx/rx switch receiver receiver sensitivity of -92dbm integrated channel filters digital demodulator for im proved sensitivity and co- channel rejection real-time digitised rssi available on hci interface fast agc for enhanced dynamic range synthesiser fully integrated synthesiser requires no external vco, varactor diode, resonator or loop filter compatible with crystals 16mhz to 26mhz or an external clock 12mhz to 52mhz physical interfaces synchronous serial inter face for system debugging i2c compatible interface to external eeprom containing device configuration data (ps key) uart interface 2 led drivers with faders auxiliary features crystal oscillator with built-in digi tal trimming power management includes digital shutdown and wake-up commands with an integrated low-power oscillator for ultra-low power park/sniff/hold mode clock request output to control external clock 2 integrated linear regulators: 1.5v output from 1.7v to 1.95v input integrated high-efficiency switch-mode regulator: 1.8v output from 2.5v to 4.4v input power-on-reset cell dete cts low-supply voltage 10-bit adc available to applications integrated charger for lithium ion/polymer batteries kalimba dsp very low-power kalimba dsp coprocessor, 64mips, 24-bit fixed point core support for sbc and mp3 codec for improved audio quality (mp3 decode functionality requires an appropriate licence from thomson, see section 17.1) single-cycle mac; 24 x 24-bi t multiply and 56-bit accumulator 32-bit instruction word, dual 24-bit data memory 6k x 32-bit program ram, 8k x 24-bit + 8k x 24-bit data ram 64 x 32-bit program memory cache when executing from rom audio codec 16-bit internal codec dac for stereo audio adc dual channel mono voice band audio integrated amplifiers for driving 16 speakers; no need for external components support for single-ended speaker termination and line output integrated low-noise microphone bias baseband and software internal rom 48kb of internal ram, allows full-speed data transfer, mixed voice/data and full piconet support logic for fec, hec, acce ss code correlation, crc, demodulation, en cryption bit stream generation, whitening and transmit pulse shaping transcoders for a-law, -l aw and linear voice from host and a-law, -law and cvsd voice over air faststream, csr low late ncy codec si gnificantly reduces the latency of the audio link, from source to sink, avoiding lip-sync i ssues when simultaneously listening to audio and watching video images configurable stereo headset rom software to set- up headset features and user interface hfp 1.5 (including 3-way calling) and hsp 1.0 support bluetooth v2.1 + edr specification secure simple pairing support bluetunes rom qfn supports as standard a new high-performance dsp based dual-microphone noise reduction bluetunes rom qfn also supports a dsp based single-microphone cvc echo and noise reduction package option qfn 68-lead, 8 x 8 x 0.9mm, 0.4mm pitch device details cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 8 of 74 _?q??=olj=nck data sheet free datasheet http:///
2 functional block diagram bluetooth modem switch-mode regulator clock generation power control and regulation sense low-voltage audio linear regulator out in en vregin_audio vdd_audio vregenable_l vregin_l en vregenable_h vss battery charger out in bat_p vdd_chg rf_p basic rate modem enhanced rate modem radio control baseband xtal_out xtal_in lo_ref vdd_lo led[0] vdd_pads rst# test_en vdd_smp_core low-voltage linear regulator out sense sense vdd_core in en vdd_ana lx i 2 c bus interface can only connect to a serial eeprom vdd_radio memory management unit microcontroller mcu interrupt controller timers system ram dsp kalimba dsp interrupt controller timers data memory dm2 program memory pm data memory dm1 internal memory interface rom programmable i/o led driver aio gpio led[1] aio[0] aio[1] pio[5:0] vdd_pio pio[14:11, 9] rf_n audio interface audio codec spkr_a_p spkr_a_n mic_bias mic_a_p mic_a_n mic_b_n mic_b_p au_ref_dcpl bluetooth v2.1 radio serial interfaces uart uart_tx uart_rx uart_cts uart_rts vdd_uart i 2 c interface pio[7] pio[8] pio[6] spi interface spi_cs# spi_miso spi_mosi spi_clk scl sda spkr_b_p spkr_b_n figure 2.1: bluetunes rom qfn functional block diagram functional block diagram cs-122312-dsp3 production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2008-2009 page 9 of 74 _?q??=olj=nck data sheet free datasheet http:///
3 package information 3.1 pinout diagram 1 2 3 4 5 6 7 8 9 10 18 19 20 11 12 13 14 15 16 17 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 68 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 top view figure 3.1: bluetunes rom qfn device pinout package information cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 10 of 74 _?q??=olj=nck data sheet free datasheet http:///
3.2 device terminal functions bluetooth radio lead pad type supply domain description rf_n 65 rf vdd_radio transmitter output/switched receiver rf_p 64 rf complement of rf_n synthesiser and oscillator lead pad type supply domain description xtal_in 3 analogue vdd_ana for crystal or external clock input xtal_out 4 drive for crystal lo_ref 5 reference voltage to decouple the synthesiser spi interface lead pad type supply domain description spi_mosi 28 input, with weak internal pull- down vdd_pads spi data input spi_cs# 30 bidirectional with weak internal pull-down chip select for spi, active low spi_clk 29 bidirectional with weak internal pull-down spi clock spi_miso 31 bidirectional with weak internal pull-down spi data output uart interface lead pad type supply domain description uart_tx 9 output, tristate, with weak internal pull-down vdd_uart uart data output, active high uart_rx 10 bidirectional with weak internal pull-down uart data input, active high uart_rts 12 bidirectional cmos output, tristate, with weak internal pull-up uart request to send active low uart_cts 11 cmos input with weak internal pull-down uart clear to send active low package information cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 11 of 74 _?q??=olj=nck data sheet free datasheet http:///
pio port lead pad type supply domain description pio[14] 20 bidirectional with programmable strength internal pull-up/down vdd_pads programmable input/output line pio[13] 19 pio[12] 18 pio[11] 15 pio[9] 14 pio[8] 21 pio[7] 22 pio[6] 23 pio[5] 24 pio[4] 25 pio[3] 58 bidirectional with programmable strength internal pull-up/down vdd_pio programmable input/output line pio[2] 59 pio[1] 60 pio[0] 61 aio[1] 6 bidirectional vdd_ana programmable input/output line aio[0] 7 package information cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 12 of 74 _?q??=olj=nck data sheet free datasheet http:///
audio lead pad type supply domain description spkr_a_n 56 analogue vdd_audio speaker output, negative, channel a spkr_a_p 57 analogue vdd_audio speaker output , positive, channel a spkr_b_n 53 analogue vdd_audio speaker output, negative, channel b spkr_b_p 54 analogue vdd_audio speaker output , positive, channel b mic_a_n 52 analogue vdd_audio microphone input, negative, channel a mic_a_p 51 analogue vdd_audio microphone input, positive, channel a mic_b_n 50 analogue vdd_audio microphone input, negative, channel b mic_b_p 48 analogue vdd_audio microphone input, positive, channel b mic_bias 45 analogue vdd_audio, bat_p microphone bias au_ref_dcpl 55 analogue vdd_audio decoupling of audio reference, for high-quality audio led drivers lead pad type supply domain description led[1] 33 open drain output open drain led driver led[0] 32 led driver test and debug lead pad type supply domain description rst# 26 input with weak internal pull- up vdd_pads reset if low. input debounced so must be low for >5ms to cause a reset. test_en 27 input with strong internal pull- down for test purposes only. leave unconnected. package information cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 13 of 74 _?q??=olj=nck data sheet free datasheet http:///
power supplies control lead description vregenable_l 68 low-voltage linear regulator and low-voltage audio linear regulator enable, active high vregin_l 1 input to internal low-voltage linear regulator vregenable_h 35 switch-mode regulator enable, active high vregin_audio 46 input to internal low-voltage audio linear regulator vdd_audio 47 positive supply for audio lx 37 switch-mode regulator output vdd_ana 2 positive supply output for analogue circuitry and 1.5v regulated output, from internal low-voltage linear regulator vdd_pio 62 positive supply for digital input/output ports pio[3:0] vdd_pads 16 positive supply for all other digital input/output ports including pio[14:11,9:4] vdd_core 17, 34 positive supply for internal digital circuitry vdd_radio 63, 66 positive supply for rf circuitry vdd_uart 13 positive supply for uart ports vdd_lo 67 positive supply for loc al oscillator circuitry bat_p 38 lithium ion/polymer battery positive terminal. battery charger output and input to switch-mode regulator. vdd_chg 39 lithium ion/polymer battery charger input vdd_smp_core 36 positive supply for switch-mode control circuitry vss exposed pad ground connections unconnected leads (ncs) description 8, 40, 41, 42, 43, 44, 49 leave unconnected package information cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 14 of 74 _?q??=olj=nck data sheet free datasheet http:///
3.3 package dimensions to p vi e w description 68-lead quad flat no-lead package size 8x8x0.9mm pitch 0.4mm dimension minimum typical maximum notes a 0.80 0.85 0.90 a1 0. 00 0.035 0.05 a2 - 0.65 0.67 a3 - 0.203 - b 0.15 0.20 0.25 d 7.90 8.00 8.05 e 7.90 8.00 8.05 e-0.40- d1 6. 10 6. 20 6.30 e1 6. 10 6. 20 6.30 f 0.35 0.40 0.45 x-1.00- y-0.85- 1 top-side polarity mark. the dimensions of the square polarity mark are 0.75 x 0.75mm. coplanarity applies to leads, corner leads and die attach pad. jedec mo-220 unit mm e exposed die attach pad 1 x y pin 1 i.d. seating plane bottom view 1 17 18 34 35 51 68 e1 d1 e f d (a3) z z z figure 3.2: bluetunes rom qfn 68 lead qfn package dimensions package information cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 15 of 74 _?q??=olj=nck data sheet free datasheet http:///
3.4 pcb design and assembly considerations this section lists recommendations to achieve maximum board-lev el reliability of the 8 x 8 x 0.9mm qfn 68-lead package: nsmd lands (lands smaller than the solder mask aperture) are pr eferred, because of the greater accuracy of the metal definition process compared to the solder mask pro cess. with solder ma sk defined pads, the overlap of the solder mask on t he land creates a step in the so lder at the land interface, which can cause stress concentration and act as a point for crack initiation. pcb land width should be 0.2mm and pcb land length should be 0. 55mm to achieve maximum reliability. solder paste must be used during the assembly process. 3.5 typical solder reflow profile see typical solder reflow profile for lead-free devices for information. package information cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 16 of 74 _?q??=olj=nck data sheet free datasheet http:///
4 bluetooth modem 4.1 rf ports 4.1.1 rf_n and rf_p rf_n and rf_p form a complementary balanced pair and are availa ble for both transmit and receive. on transmit their outputs are combined using an external balun into the sin gle-ended output required for the antenna. similarly, on receive their input signals are combined internally. both terminals present similar complex impedances that may requ ire matching networks between them and the balun. viewed from the chip, the outputs can each be modelled a s an ideal current source in parall el with a lossy capacitor. an equivalent series inductance can represent the pa ckage parasitics. g-tw-0003349.2.2 + _ pa + _ lna rf switch rf switch rf_n rf_p figure 4.1: simplified circuit rf_n and rf_p rf_n and rf_p require an external dc bias. the dc level must be set at vdd_radio. 4.2 rf receiver the receiver features a near-zero if architecture that allows t he channel filters to be integrated onto the die. sufficient out-of-band blocking specification at the lna input allows the receiver to be used in close proximity to gsm and w?cdma cellular phone transmitters without being desensitised. the use of a dig ital fsk discriminator means that no discriminator tank is needed and its excellent performance i n the presence of noise allows bluetunes rom qfn to exceed the bluetooth requirements for co-channel and adjacen t channel rejection. for edr, the demodulator contains an adc which digitises the if received signal. this information is then passed to the edr modem. 4.2.1 low noise amplifier the lna operates in differential mode and takes its input from the shared rf port. 4.2.2 rssi analogue to digital converter the adc implements fast agc. the adc samples the rssi voltage o n a slot-by-slot basis. the front-end lna gain is changed according to the measured rssi value, keeping the fi rst mixer input signal within a limited range. this improves the dynamic range of the receiver, improving performan ce in interference limited environments. bluetooth modem cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 17 of 74 _?q??=olj=nck data sheet free datasheet http:///
4.3 rf transmitter 4.3.1 iq modulator the transmitter features a direct iq modulator to minimise freq uency drift during a transm it timeslot, which results in a controlled modulation index. digital baseband transmit cir cuitry provides the required spectral shaping. 4.3.2 power amplifier the internal pa has a maximum output power that allows bluetune s rom qfn to be used in class 2 and class 3 radios without an external rf pa. 4.4 bluetooth radio synthesiser the bluetooth radio synthesiser is fully integrated onto the di e with no requirement for a n external v co screening can, varactor tuning diodes, lc resonators or loop filter. the synthesiser is guaranteed to lock in sufficient time across the guaranteed temperature range to meet the bluetooth v 2.1 + edr specification. 4.5 baseband 4.5.1 burst mode controller during transmission the bmc constructs a packet from header inf ormation previously lo aded into memory-mapped registers by the software and payload data/voice taken from the appropriate ring buffer in the ram. during reception, the bmc stores the packet header in memory-mapped registers and the payload data in the appropriate ring buffer in ram. this architecture minimises the intervention required b y the processor during transmission and reception. 4.5.2 physical layer hardware engine 4.6 basic rate modem the basic rate modem satisfies the basic data rate requirements of the bluetooth v2.1 + edr specification. the basic rate was the standard data rate available on the bluetoot h v1.2 specification and below, it is based on gfsk modulation scheme. including the basic rate modem allows bluetunes rom qfn compati bility with earlier bluetooth products. the basic rate modem uses the rf ports, receiver, transmitter a nd synthesiser, alongside the baseband components described in section 4.5. 4.7 enhanced data rate modem the edr modem satisfies the requirements of the bluetooth v2.1 + edr specification. edr has been introduced to provide 2x and 3x data rates with minimal disruption to high er layers of the bluetooth stack. bluetunes rom qfn supports both the basic and enhanced data rates and is complian t with the bluetooth v2.1 + edr specification. at the baseband level, edr uses the same 1.6khz slot rate and t he 1mhz symbol rate defined for the basic data rate. edr differs in that each symbol in the payload portion of a packet represents 2 or 3 bits. this is achieved using 2 new distinct modulation schemes. table 4.1 and figure 4.2 sum marise these. link establishment and management are unchanged and still use gfsk for both the header and payloa d portions of these packets. the enhanced data rate modem uses the rf ports, receiver, trans mitter and synthesiser, with the baseband components describ ed in section 4.5. data rate scheme bits per symbol modulation basic rate 1 gfsk edr 2 /4 dqpsk edr 3 8dpsk (optional) table 4.1: data rate schemes bluetooth modem cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 18 of 74 _?q??=olj=nck data sheet free datasheet http:///
g-tw-0000244.2.3 access code access code header header payload guard sync payload trailer basic rate enhanced data rate /4 dqpsk or 8dpsk figure 4.2: bdr and edr packet structure bluetooth modem cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 19 of 74 _?q??=olj=nck data sheet free datasheet http:///
5 clock generation bluetunes rom qfn requires a bluetooth reference clock frequenc y of 12mhz to 52mhz from either an externally connected crystal o r from an extern al tcxo source. all bluetunes rom qfn internal digital clo cks are gene rated usi ng a phase locked loop, which is locked to the frequency of either the external 12mhz to 52mhz reference clock source or an internally generated watchdog clock frequency of 1khz. the bluetooth operation determines the use of the watchdog cloc k in low-power modes. 5.1 clock architecture g-tw-0000189.3.3 bluetooth radio auxiliary pll digital circuitry reference clock figure 5.1: clo ck architecture 5.2 input frequencies and ps key settings bluetunes rom qfn is configured to operate with a chosen refere nce frequency. this reference frequency is set by pskey_ana_freq for all frequen cies using an in teger multiple of 250khz. the input frequency default setting for bluetunes rom qfn is 26mhz depending on the software build. full details are in the software release note for the specif ic build from www.csrsupport.com . 5.3 external reference clock 5.3.1 input: xtal_in the external reference clock is applied to the bluetunes rom qf n xtal_in input. bluetunes rom qfn is configured to accept the external reference clock at xtal_in by connecting xtal_out to ground. the external clock can be either a digital level square wave or sinusoidal, and this may be directly coupled to xtal_in without the need for additional components. a digital level ref erence clock gives superior noise immunity, as the high slew rate clock edges have lower voltage to phase conversion. i f peaks of the reference clock are either below vss or above vdd_ana, it must be driven through a dc blocking capac itor (approximately 33pf) connected to xtal_in. the external reference clock signal should meet the specificati ons in table 5.1. clock generation cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 20 of 74 _?q??=olj=nck data sheet free datasheet http:///
min typ max unit frequency (a) 12 26 52 mhz duty cycle 20:80 50:50 80:20 - edge jitter (at zero crossing) - - 15 ps rms signal level ac coupled sinusoid 0.4 - vdd_ana (b) v pk-pk dc coupled digital v il - vss (c) - v v ih - vdd_ana (b) (c) - v table 5.1: external clock specifications (a) the frequency should be an integer multiple of 250khz except fo r the cdma/3g frequencies (b) vdd_ana is 1.50v nominal (c) if driven via a dc blocking cap acitor max amplitude is reduced to 750mv pk-pk for non 50:50 duty cycle 5.3.2 xtal_in impedance in external mode the impedance of xtal_in does not change significantly between operating modes, typically 10ff. when transitioning from deep sleep to an active state a spike of up to 1pc may be measured. for this reason csr recommends that a buffere d clock input is used. 5.3.3 clock start-up delay bluetunes rom qfn hardware incorporates an automatic 5ms delay after the assertion of t he system clock request signal before running firmware, see figure 5.2. this is suitabl e for most applications using an external clock source. however, there may be scenarios where the clock cannot be guara nteed to either exist or be stable after this period. under these conditions, bluetunes rom qfn firmware provides a s oftware function that extends the system clock request signal by a period stor ed in pskey_clock_startup_delay. this value is set in milliseconds from 1ms to 31ms. zero is the default entry for 5ms delay. this ps key allows the designer to optimise a system where cloc k latencies may be longer than 5ms while still keeping the current consumption of bluetunes rom qfn as low as possible. bluetunes rom qfn consumes about 2ma of current for the duration of pskey_clock_startup_de lay before activat ing the firmware. 5.3.4 clock timing accuracy as figure 5.2 shows, the 250ppm timing accuracy on the external clock is required 2ms after the firmware begins to run. this is to guarantee that the firmware can maintain tim ing accuracy in accordance with the bluetooth v2.1 + edr specification. radio activity may occur after 6ms after the firmware starts. therefore, at this point the timing accuracy of the external clock source must be within 20ppm. clock generation cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 21 of 74 _?q??=olj=nck data sheet free datasheet http:///
g-tw-0000190.3.2 clock accuracy 0 20ppm 6 250ppm 2 1000ppm ms after firmware clk_req firmware activity pskey_clock_startup_delay firmware activity radio activity figure 5.2: tcxo clock accuracy 5.4 crystal oscillator: x tal_in and xtal_out bluetunes rom qfn contains a cryst al driver circuit. this opera tes with an exter nal crystal and cap acitors to form a pierce oscillator. the external crystal i s connected to pins xtal_in, xtal_out. g-tw-0000191.3.2 - g m c trim c int c t2 c t1 xtal_out xtal_in figure 5.3: cryst al driver circuit figure 5.4 shows an electrical e quivalent circu it for a crystal . the crystal appears induc tive near its resonant frequency. it forms a resonant circuit with its load capacitors . clock generation cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 22 of 74 _?q??=olj=nck data sheet free datasheet http:///
g-tw-0000245.4.4 l m r m c m c o figure 5.4: crystal e quivalen t circuit the resonant frequ ency may be trimmed with the crystal load cap acitance. bluetunes rom qfn contains variable internal capacitors to provide a fine trim. parameter min typ max unit frequency 16 26 26 mhz initial tolerance - 25 - ppm pullability - 20 - ppm/pf table 5.2: crystal specification the bluetunes rom qfn driver circuit is a transconductance ampl ifier. a voltage at xtal _in generate s a current at xtal_out. the value of transconductance is variable and may be set for optimum performance. 5.4.1 load capacitance for resonance at the correct frequency th e crystal shou ld be lo aded with its specified load capacitance, which is defined for the crystal. this is the total capacitance across t he crystal viewed from its t erminals. bluetunes rom qfn provides some of this load with the capacitors c trim and c int . the remainder should be from the external capacitors labelled c t1 and c t2 . c t1 should be three times the value of c t2 for best noise performance. this maximises the signal swing and slew rate at xtal_in (to which all on-chip clocks are referred). crystal load ca pacitance, c l is calculated using equation 5.1: c l =c int + (c t2 +c trim )c t1 c t2 +c trim +c t1 equation 5.1: load capacitance note: c trim = 3.4pf nominal (mid-range setting) c int = 1.5pf c int does not include the crystal internal self capacitance; it is the driver self capacitance. 5.4.2 frequency trim bluetunes rom qfn enables frequency adjustments to be made. thi s feature is typically used to remove initial tolerance frequency errors associated with the crystal. frequen cy trim is achieved by adjusting the crystal load capacitance with an on-chip trim capacitor, c trim . the value of c trim is set by a 6-bit word in pskey_ana_ftrim. its value is calculated as follows: c trim = 125ff pskey_ana_ftrim equation 5.2: trim capacitance clock generation cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 23 of 74 _?q??=olj=nck data sheet free datasheet http:///
the c trim capacitor is connected between xtal_in and ground. when viewed from the crystal terminals, the combination of the tank capacitors and the trim capacitor prese nts a load across the term inals of the crystal which varies in steps of typically 125ff for each least significant b it increment of pskey_ana_ftrim. equation 5.3 describes the frequency trim. (f x ) f x =pullability0.110 ( c t1 c t1 +c t2 +c trim ) (ppm/lsb) equation 5.3: frequency trim note: f x = crystal frequency pullability is a crystal parameter with units of ppm/pf total trim range is 0 to 63 if not specified, the pullability of a crystal may be calculate d from its motional capacitance with equation 5.4. () () () 2 0 i i m x x c c c 2 c f f + = ? ? ? equation 5.4: pullability note: c 0 = crystal self capacitance (shunt capacitance) c m = crystal motional capacitance (series branch capacitance in c rystal model), see figure 5.4 it is a bluetooth requirement that the frequency is always with in 20ppm. the trim range should be sufficient to pull the crystal within 5ppm of the exact frequency. this leav es a margin of 15ppm for frequency drift with ageing and temperature. a crystal with an ageing and temperatur e drift specification of better than 15ppm is required. 5.4.3 transconductance driver model the crystal and its load capacitors should be viewed as a trans impedance element, whereby a current applied to one terminal generates a voltage at the other. the transconduct ance amplifier in bluetunes rom qfn uses the voltage at its input, xtal_in, to generate a current at its out put, xtal_out. therefore, the circuit oscillates if the transconductance, transimpedance product is greater than unity. for sufficient oscillation amplitude, the product should be greater than three. the transconductance required for oscillation is defined by the relationship shown in equation 5.5. g m >3 (2f x ) 2 r m ((c 0 +c int )(c t1 +c t2 +c trim )+c t1 (c t2 +c trim )) c t1 (c t2 +c trim ) equation 5.5: transconductance required for oscillation bluetunes rom qfn guarantees a transconductance value of at lea st 2ma/v at maximum drive level. note: more drive strength is required for higher frequency crystals, higher loss crystals (larger r m ) or higher capacitance loading optimum drive level is attained when the level at xtal_in is ap proximately 1v pk-pk. the drive level is determined by the crystal driver transconductance. 5.4.4 negative resistance model an alternative representation of the crystal and its load capac itors is a frequency dependent resistive element. the driver amplifier may be considered as a circuit that provides n egative resistance. for oscillation, the value of the negative resistance must be greater than that of the crystal ci rcuit equivalent resistance. although the bluetunes rom qfn crystal driver circuit is based on a transimp edance amplifier, it is possible to calculate an equivalent negative resistance for it using the formula in equa tion 5.6. clock generation cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 24 of 74 _?q??=olj=nck data sheet free datasheet http:///
r neg > c t1 (c t2 +c trim ) g m (2f x ) 2 (c 0 +c int )((c t1 +c t2 +c trim )+c t1 (c t2 +c trim )) 2 equation 5.6: equivalent negative resistance equation 5.6 shows the negative resistance of the bluetunes rom qfn driver as a function of its drive strength. the value of the driver negative resistance may be easily measu red by placing an additional resistance in series with the crystal. the maximum value of this resistor (oscillati on occurs) is the equivalent negative resistance of the oscillator. 5.4.5 crystal ps key settings the bluetunes rom qfn firmware automatically controls the drive level on the crystal circuit to achieve optimum input swing. pskey_xtal _target_amplitude is used by the firmwar e to servo the required amplitude of crystal oscillation. refer to the software build release note for a det ailed description. configure the bluetunes rom qfn to operate with the chosen refe rence frequency. clock generation cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 25 of 74 _?q??=olj=nck data sheet free datasheet http:///
6 bluetooth stack microcontroller a 16-bit risc mcu is used for low power consumption and efficie nt use of memory. the mcu, interrupt controller and event timer run the bluetooth software stack and control the bluetooth radio and host interfaces. 6.1 programmable i/o ports, pio and aio bluetunes rom qfn contains 14 lines of programmable bidirection al i/o. bluetunes rom qfn has 2 general-purpose analogue interface pins , aio[1:0], used to access internal circuitry and control signals. auxiliary functions available on the analogue interface include a 10-bit adc. note: the pio and aio configuration is dependent on the bluetunes rom stereo headset solution. pio[14:11,9:4] are powered from vdd_pads and pio[3:0] are power ed from vdd_pio. aio[1:0] are powered from vdd_ana. bluetooth stack microcontroller cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 26 of 74 _?q??=olj=nck data sheet free datasheet http:///
7 kalimba dsp the kalimba dsp is an open platformdsp allowing signal processi ng functions to be performed on over-air data or codec data in order to enhance audio applications. noise cancel lation and audio enhancement algorithms are hard- coded into the rom. figure 7.1 shows the kalimba dsp interfaces to other functional blocks within bluetunes rom qfn. g-tw-0001399.6.2 dsp rams memory management unit mcu register interface (including debug) kalimba dsp core dm2 dm1 pm instruction decode program flow debug data memory interface address generators alu clock select pio internal control registers mmu interface interrupt controller timer mcu window flash window dsp mmu port dsp data memory 2 interface (dm2) dsp data memory 1 interface (dm1) dsp program memory interface (pm) registers programmable clock = 64mhz pio in/out irq to subsystem irq from subsystem 1s timer clock dsp program control dsp, mcu and memory window control figure 7.1: kalimba dsp interface to internal functions the key features of the dsp include: 64mips performance, 24-bit fixed point dsp core single cycle mac of 24 x 24-bit multiply and 56-bit accumulate 32-bit instruction word separate program memory and dual data memory, allowing an alu o peration and up to two memory accesses in a single cycle zero overhead looping zero overhead circular buffer indexing single cycle barrel shifter with up to 56-bit input and 24-bit output multiple cycle divide (performed in the background) bit reversed addressing orthogonal instruction set low overhead interrupt kalimba dsp cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 27 of 74 _?q??=olj=nck data sheet free datasheet http:///
8 memory interface and management 8.1 memory management unit the mmu provides a number of dynamically allocated ring buffers that hold the data that is in transit between the host, the air or the kalimba dsp. the dynamic allocation of mem ory ensures efficient use of the available ram and is performed by a hardware mmu to minimise the overheads on the processor during data/voice transfers. 8.2 system ram 48kb of on-chip ram supports the risc mcu and is shared between the ring buffers used to hold voice/data for each active connection and the general-purpose memory required by the bluetooth stack. 8.3 kalimba dsp ram additional on-chip ram is provided to support the kalimba dsp: 8k x 24-bit for data memory 1 (dm1) 8k x 24-bit for data memory 2 (dm2) 6k x 32-bit for program memory (pm) note: the kalimba dsp can also execute directly from internal rom, us ing a 64-instruction on-chip cache. 8.4 internal rom internal rom is prov ided for system firmw are implementation. memory interface and management cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 28 of 74 _?q??=olj=nck data sheet free datasheet http:///
9 serial interfaces 9.1 uart interface bluetunes rom qfn has a standard uart serial interface that pro vides a simple mechanism for communicating using rs232 protocol. g-tw-0000198.2.3 uart_tx uart_rx uart_rts uart_cts figure 9.1: universal asynchronous receiver figure 9.1 shows the 4 signals that implement the uart function . when bluetunes rom qfn is connected to another digital device, uart_rx and uart_tx transfer data betwe en the 2 devices. the remaining 2 signals, uart_cts and uart_rts, can implement rs232 hardware flow contro l where both are active low indicators. uart configuration parameters, such as baud rate and packet for mat, are set using bluetunes rom qfn firmware. note: to communicate with the uart at its maximum data rate using a s tandard pc, an accelerated serial port adapter card is required for the pc. parameter possible values baud rate minimum 1200 baud (2%error) 9600 baud (1%error) maximum 4mbaud (1%error) flow control rts/cts or none parity none, odd or even number of stop bits 1 or 2 bits per byte 8 table 9.1: possible uart settings the uart interface can reset bluetunes rom qfn on reception of a break signal. a break is identified by a continuous logic low (0v) on the uart_rx terminal, as shown in figure 9.2. if t brk is longer than the value, defined by pskey_hostio_uart_reset_timeou t a reset occurs. this feature allows a host to init ialise the system to a known state. also, bluetunes rom qfn can emit a break charact er that may be used to wake the host. serial interfaces cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 29 of 74 _?q??=olj=nck data sheet free datasheet http:///
g-tw-0000250.3.2 uart_tx t brk figure 9.2: break signal table 9.2 shows a list of commonly used baud rates and their as sociated values for pskey_uart_baudrate. there is no requirement to use these standard values. any baud rate within the supported range can be set in the ps key according to the formula in equation 9.1. baud rate = pskey_uart_baudrate 0.004096 equation 9.1: baud rate baud rate persistent store value error hex dec 1200 0x0005 5 1.73% 2400 0x000a 10 1.73% 4800 0x0014 20 1.73% 9600 0x0027 39 -0.82% 19200 0x004f 79 0.45% 38400 0x009d 157 -0.18% 57600 0x00ec 236 0.03% 76800 0x013b 315 0.14% 115200 0x01d8 472 0.03% 230400 0x03b0 944 0.03% 460800 0x075f 1887 -0.02% 921600 0x0ebf 3775 0.00% 1382400 0x161e 5662 -0.01% 1843200 0x1d7e 7550 0.00% 2764800 0x2c3d 11325 0.00% 3686400 0x3afb 15099 0.00% table 9.2: standard baud rates serial interfaces cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 30 of 74 _?q??=olj=nck data sheet free datasheet http:///
9.1.1 uart configuration while reset is active the uart interface is tristate while bluetunes rom qfn is being held in reset. this allows the user to daisy chain devices onto the physi cal uart bus. the constraint on this meth od is that any devices connected to this bus must tristate when bluetunes rom qfn reset is de-asserted and the fi rmware begins to run. 9.2 programming and debug interface bluetunes rom qfn uses a 16-bit data and 16-bit address program ming and debug interface. transactions can occur when the internal processor is running or is stopped. data may be written or read one word at a time, or the auto-inc rement feature is avai lable for bl ock access. 9.2.1 instruction cycle the bluetunes rom qfn is the slave and receives commands on spi _mosi and outputs data on spi_miso. table 9.3 shows the instruction cycle for a spi transaction. 1 reset the spi interface hold spi_cs# high fo r two spi_clk cycles 2 write the command word take spi_cs# low and cl ock in the 8-bit command 3 write the address clock in the 16-bit address word 4 write or read data words clock in or out 16-bit data word(s) 5 termination take spi_cs# high table 9.3: instruction cycle for a spi transaction with the exception of reset, spi_cs# must be held low during th e transaction. data on s pi_mosi is clocked into the bluetunes rom qfn on the rising edge of the clock line spi_ clk. when reading, bluetunes rom qfn replies to the master on spi_miso with the data changing on the falling edge of the spi_clk. the master provides the clock on spi_clk. the transaction is terminated b y taking spi_c s# high. sending a command word and the address of a register for every time it is to be read or written is a significant overhead, especially when large am ounts of data are to be trans ferred. to overcome this bluetunes rom qfn offers increased data transfer efficiency via an auto increment operation. to invoke auto increment, spi_cs# is kept low, which auto increments the address, while providing an extr a 16 clock cycles for each extra word to be written or read. 9.2.2 multi-slave operation bluetunes rom qfn should not be connected in a multi-slave arra ngement by simple parallel connection of slave miso lines. when bluetunes rom qfn is deselected (spi_cs# = 1), the spi_miso line does not float. instead, bluetunes rom qfn outputs 0 if the processor is running or 1 if it is stopped. 9.3 i 2 c interface pio[8:6] is available to form a master i2c interface. the inter face is formed using software to drive these lines. note: the program memory for the bluetu nes rom qfn is internal rom so the i2c interface can only connect to a serial eeprom, an examp le is shown in figur e 9.3. the eeprom st ores ps keys and configuration information. eeprom supply in figure 9.3 is 1.8v. serial interfaces cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 31 of 74 _?q??=olj=nck data sheet free datasheet http:///
g-tw-0000207.5.3 s e r i a l e e p r o m ( 2 4 a a 3 2 ) 4 3 2 1 5 6 7 8 pio[8] pio[7] pio[6] vcc wp scl sda a0 a1 a2 gnd decoupling capacitor eeprom supply figure 9.3: exampl e eeprom connection serial interfaces cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 32 of 74 _?q??=olj=nck data sheet free datasheet http:///
10 audio interface the bluetunes rom qfn audio interface circuit consists of: stereo audio dac and outputs dual channel mono voice band adc with dual microphone inputs the audio interface supports all requirements of the bluetunes rom stereo headset solution and figure 10.1 shows the functional b locks of the bluet unes rom qfn a udio interface. the audio interface supports stereo playback of audio signals at multiple sample rates with 16-bit resolution. audio codec memory management unit mmu voice port mcu register interface voice port registers stereo audio dac driver dac a adc b adc a dac b dual channel voice adc input figure 10.1: bluetunes rom qfn audio interface 10.1 audio input and output the audio input circuitry consists of a dual audio input that c an be configured to be either single-ended or fully differential and programmed for either microphone or line input . it has an analogue and digital programmable gain stage for optimisation of different microphones. the audio output circuitry consists of a dual differential clas s a-b output stage. 10.2 audio codec interface the main features of the interface are: stereo and mono analogue output for voice band and audio band dual mono analogue microphone input for voice band important note: to avoid any confusion regarding stereo operation this data she et explicitly states which is the left and right channel for audio output. with respect to software and any regi sters, channel 0 or channel a represents the left channel and channel 1 or channel b represents the right channel for output. audio interface cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 33 of 74 _?q??=olj=nck data sheet free datasheet http:///
10.2.1 audio codec block diagram digital circuitry input amplifier mic_b_p mic_b_n - a dc ? output amplifier lp filter spkr_a_p spkr_a_n - dac ? output amplifier lp filter spkr_b_p spkr_b_n - dac ? input amplifier mic_a_p mic_a_n - a dc ? stereo audio and voice band audio output dual channel mono voice band audio input figure 10.2: codec audio input and output stages the audio codec uses a fully differential architecture in the a nalogue signal path, which results in low noise sensitivity and good power supply rejection while effectively doubling the signal amplitude. it operates from a single power- supply of 1.5v and uses a minimum of external components. 10.2.2 adc the adc consists of: 2 second-order sigma delta converters allowing two separate cha nnels that are identical in functionality, as shown in figure 10.2. 2 gain stages for each channel, one of which is an analogue gai n stage and the other is a digital gain stage. 10.2.3 adc sample rate each adc supports 8khz sample rate only. 10.2.4 adc digital gain the digital gain stage has a programmable selection value in th e range of 0 to 15 with the associated adc gain settings summarised in table 10.1. there is also a high resolut ion digital gain mode that allows the gain to be changed in 1/32 steps. contact csr for more information. audio interface cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 34 of 74 _?q??=olj=nck data sheet free datasheet http:///
gain selection value adc digital gain setting (db) gain selection value adc digital gain setting (db) 0 0 8 -24 1 3.5 9 -20.5 2 6 10 -18 3 9.5 11 -14.5 4 12 12 -12 5 15.5 13 -8.5 6 18 14 -6 7 21.5 15 -2.5 table 10.1: adc digital gain rate selection 10.2.5 adc analogue gain figure 10.3 shows the equivalent block diagram for the adc anal ogue amplifier. it is a two-stage amplifier: the first stage amplifier has a selectable gain of either bypas s for line input mode or gain of 24db gain for the microphone mode. the second stage has a programmable gain with 7 individual 3db steps. by combining the 24db gain selection of the microphone input with the 7 individual 3db gai n steps, the overall range of the analogue amplifier is approximately -3db to 42db in 3db steps. the bluet unes rom stereo headset solution controls all the gain control of the adc. g-tw-0001400.4.2 bypass or 24db gain line mode / mic mode switches shown for line mode microphone mode input impedance = 6k line mode input impedance = 6k to 30k gain 0:7 -3db to 18db gain p n p n figure 10.3: adc analogue amplifier block diagram 10.2.6 dac the dac consists of: 2 second-order sigma delta converters allowing 2 separate chann els that are identical in functionality, as figure 10.2 shows. 2 gain stages for each channel: one is an analogue gain stage a nd the other is a digital gain stage. audio interface cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 35 of 74 _?q??=olj=nck data sheet free datasheet http:///
10.2.7 dac sample rate selection each dac supports the following samples rates: 8khz 11.025khz 12khz 16khz 22.050khz 24khz 32khz 44.1khz 48khz 10.2.8 dac digital gain the digital gain stage has a programmable selection value in th e range of 0 to 15 with associated dac gain settings, summarised in table 10.2. there is also a high resolution digit al gain mode that allows the gain to be changed in 1/32db steps. contact csr for more information. the overall gain control of the dac is controlled by the bluetu nes rom stereo headset solution. its setting is a combined function of the digital and analogue amplifier setting s. digital gain selection value dac digital gain setting (db) digital gain selection value dac digital gain setting (db) 0 0 8 -24 1 3.5 9 -20.5 2 6 10 -18 3 9.5 11 -14.5 4 12 12 -12 5 15.5 13 -8.5 6 18 14 -6 7 21.5 15 -2.5 table 10.2: dac digital gain rate selection 10.2.9 dac analogue gain table 10.3 shows the dac analogue gain stage consists of 8 gain selection values that represent seven 3db steps. the bluetunes rom stereo headset solution controls the overall gain control of the dac. its setting is a combined function of the digital and analogue amplifier settings. analogue gain selection value dac analogue gain setting (db) analogue gain selection value dac analogue gain setting (db) 7 3 3 -9 6 0 2 -12 5 -3 1 -15 4 -6 0 -18 table 10.3: dac analogue gain rate selection audio interface cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 36 of 74 _?q??=olj=nck data sheet free datasheet http:///
10.2.10 microphone input figure 10.4 shows recommended biasing for each microphone. the microphone bias, mic_bias, derives its power from the bat_p and requires a 1f capacitor on its output. r2 c2 r1 c1 microphone bias c3 c4 mic_a_p mic_a_n mic1 + input amplifier figure 10.4: microphone biasing (single channel shown) the mic_bias is like any voltage regulator and requires a minim um load to maintain regulation. the mic_bias maintains regulation within the limits 0.200ma to 1.230ma. if t he microphone sits below these limits, then the microphone output must be pre-loaded with a large value resisto r to ground. the audio input is intended for use in the range from 1a @ 94d b spl to about 10a @ 94db spl. with biasing resistors r1 and r2 equal to 1k, this requires microphones wit h sensitivity between about C40dbv and C60dbv. the input impedance at mic_a_n, mic_a_p, mic_b_n and mic_b_p is typically 6.0k. c1 and c2 should be 150nf if bass roll-off is required to limit wind noise on the microphone. r1 sets the microphone load impedance and is normally in the ra nge of 1k to 2k. r2, c3 and c4 improve the supply rejection by decoupling supply noise from the microphone. values should be selected as required. r2 may be connected to a convenient suppl y, in which case the bias network is permanently enabled, or to the mic_bias output (which is ground referenced and provides good rejection of the supply), which may be configured to provide bias only when the microphone is r equired. table 10.4 shows the 4-bit programmable output voltage that the microphone bias provides, and table 10.5 shows the 4-bit programmable output current. the characteristics of the microphone bias include: power supply: bluetunes rom qfn microphone supply is bat_p minimum input voltage = output voltage + drop-out voltage maximum input voltage is 4.4v typically the microphone bias is at the same level as vdd_audio (1.5v) drop-out voltage: 300mv minimum guaranteed for configuration of voltage or current output shown in table 10.4 and table 10.5 output voltage: 4-bit programmable between 1.7v to 3.6v tolerance 90 to 110% output current: 4-bit programmable from 200a to 1.230ma maximum current guaranteed to be >1ma load capacitance: unconditionally stable for 1f 20% and 2.2f 20% pure c audio interface cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 37 of 74 _?q??=olj=nck data sheet free datasheet http:///
output step vol_set[3:0] min typ max units 0 0000 - 1.71 - v 1 0001 - 1.76 - v 2 0010 - 1.82 - v 3 0011 - 1.87 - v 4 0100 - 1.95 - v 5 0101 - 2.02 - v 6 0110 - 2.10 - v 7 0111 - 2.18 - v 8 1000 - 2.32 - v 9 1001 - 2.43 - v 10 1010 - 2.56 - v 11 1011 - 2.69 - v 12 1100 - 2.90 - v 13 1101 - 3.08 - v 14 1110 - 3.33 - v 15 1111 - 3.57 - v table 10.4: voltage output steps audio interface cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 38 of 74 _?q??=olj=nck data sheet free datasheet http:///
output step cur_set[3:0] typ units 0 0000 0.200 ma 1 0001 0.280 ma 2 0010 0.340 ma 3 0011 0.420 ma 4 0100 0.480 ma 5 0101 0.530 ma 6 0110 0.610 ma 7 0111 0.670 ma 8 1000 0.750 ma 9 1001 0.810 ma 10 1010 0.860 ma 11 1011 0.950 ma 12 1100 1.000 ma 13 1101 1.090 ma 14 1110 1.140 ma 15 1111 1.230 ma table 10.5: current output steps note: for bat_p, the psrr at 100hz to 22khz, with >300mv supply headr oom, decoupling capacitor of 1.1f, is typically 58.9db and worst case 53.4db. for vdd_audio, the psrr at 100hz to 22khz, decoupling capacitor of 1.1f, is typically 88db and worst case 60db. 10.2.11 line input if the input analogue gain is set to less than 24db, bluetunes rom qfn automatically selects line input mode. in line input mode the first stage of the amplifier is automatical ly disabled, providing additional power saving. in line input mode the input impedance varies from 6k to 30k, dependi ng on the volume setting. figure 10.5 and figure 10.6 show 2 circuits for line input operation and show connecti ons for either differential or single-ended inputs. c1 c2 mic_a_p mic_a_n figure 10.5: differential input (single channel shown) audio interface cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 39 of 74 _?q??=olj=nck data sheet free datasheet http:///
c1 c2 mic_a_p mic_a_n figure 10.6: single-ended input (single channel shown) 10.2.12 output stage the output stage digital circuitry converts the signal from 16- bit per sample, linear pcm of variable sampling frequency to bit stream, which is fed into the analogue output circuitry. the output stage circuit comprises a dac with gain setting and class ab output stage amp lifier. the output is available as a differe ntial signal b etween spkr_a_n and spkr_a_ p for the left channel, as figure 10.7 shows, and between spkr_b_n and spkr_b_p for the right channel. the output stage is capable of driving a speaker directly when its impedance is at least 8 and an external regulator is used, but this will be at a reduced output swing. spkr_a_p spkr_a_n figure 10.7: speaker output (single channel shown) a 3-bit programmable resistive divider controls the analogue ga in of the output stage, which sets the gain in steps of approximately 3db. 10.2.13 mono operation mono operation is a single-channel operation of the stereo code c. the left channel represents the single mono channel for audio in and audio out. in mono operation the right channel is the auxiliary mono channel that may be used in dual mono channel operation. in single channel mono operation, disable the other channel to reduce power consumption. important note: for mono operation this data sheet uses the left channel for st andard mono operation for audio input and output and with respect to software and any registers, channel 0 or ch annel a represents the standard mono channel for audio input and output. in mono operation the second channe l which is the right channel, channel 1 or channel b can be used as a second mono channel if required and this cha nnel is referred to as the auxiliary mono channel for audio input and output. 10.2.14 side tone in some applications it is necessary to implement side tone. th is involves feeding an attenuated version of the microphone signal to the earpiece. the bluetunes rom qfn codec contains side tone circuitry to do this. the side tone hardware is configured through the following ps keys: pskey_side_tone_enable pskey_side_tone_gain pskey_side_tone_after_adc pskey_side_tone_after_dac audio interface cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 40 of 74 _?q??=olj=nck data sheet free datasheet http:///
10.2.15 integrated digital filter bluetunes rom qfn has a programmable digital filter integrated into the adc channel of the codec. the filter is a 2 stage, second order iir and is used for functions such as cus tom wind noise rejection. the filter also has optional dc blocking. the filter has 10 configuration words used as follows: 1 for gain value 8 for coefficient values 1 for enabling and disabling the dc blocking the gain and coefficients are all 12-bit 2's complement signed integer with the format xx.xxxxxxxxxx note: the position of the binary point is between bit[10] and bit[9], where bit[11] is the most significant bit. for example: 01.1111111111 = most positive number, close to 2 01.0000000000 = 1 00.0000000000 = 0 11.0000000000 = -1 10.0000000000 = -2 , most negative number equation 10.1 shows the equation for the iir filter. equation 1 0.2 shows the equation for when the dc blocking is enabled. the filter can be configured, enabled and disabled from the vm via the codecsetiirfiltera and codecsetiirfilterb traps. this requires firmware support. the configuration funct ion takes 10 variables in the order shown below: 0 :gain 1 : b 01 2 : b 02 3 : a 01 4 : a 02 5 : b 11 6 : b 12 7 : a 11 8 : a 12 9 : dc block (1 = enable, 0 = disable) audio interface cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 41 of 74 _?q??=olj=nck data sheet free datasheet http:///
filter, h(z) = gain ( 1+b 01 z ?1 +b 02 z ?2 ) ( 1+a 01 z ?1 +a 02 z ?2 ) ( 1+b 11 z ?1 +b 12 z ?2 ) ( 1+a 11 z ?1 +a 12 z ?2 ) equation 10.1: iir filter transfer function, h(z) filter with dc blocking, h dc (z) = h(z) ( 1?z ?1 ) equation 10.2: iir filter plus dc blocking transfer function, h dc (z) 10.3 auristream codec the auristream codec is an adpcm codec and works on the princip le of transmitting the difference between the actual value of the signal and a prediction rather than the sig nal itself. therefore, the information transmitted is reduced along with the power requirement. the quality of the ou tput depends on the number of bits used to represent the sample. note: the use of the auristrea m codec is as follows: the auristream codec is an alternative to standard cvsd it requires csr devices supporting auristream at both ends of t he link auristream is negotiated when the link is brought up. if either end does not support auristream the system will switch to standard cvsd ensuri ng full inte roperabil ity with any non-auristream bluetooth devices. the inclusion of the auristream codec can greatly enhance audio quality in the wideband mode and results in reduced power consumption compared to a cvsd implementation whe n used at both ends of the system. the auristream codec on bluetunes rom qfn supports only one g72 6 mode of operation 4-bit, 8khz sample rate, 32kbps mode 1 gives 30% reduced power in both handset and headset blue tooth ics audio interface cs-122312-dsp3 production information this material is subject to csr's non-disclosure agreement ? cambridge silicon radio limited 2008-2009 page 42 of 74 _?q??=olj=nck data sheet free datasheet http:///
11 power control and regulation bluetunes rom qfn contains 3 regulators: 1 switch-mode regulator generates a 1.8v rail for the chip i/os 2 low-voltage linear regulators which run in parallel to supply the 1.5v core supplies from the 1.8v rail various configurations for power control and regulation with bl uetunes rom qfn are as follows: powered from the switch-mode regulator and the low-voltage line ar regulators in series, as figure 11.1 shows powered directly from an external 1.8v rail, omitting the switc h-mode regulator powered from an external 1.5v rail omitting all regulators vdd_chg vdd_smp_core lx switch-mode regulator sense en lx battery charger out in 1.8v rail low-voltage audio linear regulator out in en low-voltage linear regulator out sense sense in en bat_p vss vregenable_h vregenable_l vregin_l vregin_audio vdd_ana vdd_audio l1 c1 figure 11.1: voltage regulator configuration 11.1 power sequencing the 1.50v supply rails are vdd_ana, vdd_lo, vdd_radio, vdd_audi o and vdd_core. csr recommends that these supply rails are all powered at the same time. the digital i/o supply rails are vdd_pio, vdd_pads and vdd_uart . the sequence of powering the 1.50v supply rails relative to the digital i/o supply rails is not important. if the digital i/o supply rails are powered before the 1.50v supply rails, all digital i/os will have a weak pull-down irrespective of the reset state. vdd_ana, vdd_lo, vdd_radio and v dd_audio can connect directly t o a 1.50v supply. a simple rc filter is recommended for vdd_core to reduce transi ents fed back onto the power supply rails. the digital i/o supply rails are connected either together or i ndependently to an appropriate voltage rail. decoupling of the digital i/o suppl y rails is recommended. 11.2 external voltage source if any of the supply rails for bluetunes rom qfn are supplied f rom an external voltage source, rather than one of the internal voltage regulators, csr recommends that vdd_lo, vd d_radio and vdd_audio should have less than 10mv rms noise levels between 0 and 10mhz. also avoid sing le tone frequencies. power control and regulation cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 43 of 74 _?q??=olj=nck data sheet free datasheet http:///
the transient response of any external regulator used should ma tch or be better than the internal regulator available on bluetunes rom qfn. for more information, refer to regulator characteristics in section 13. it is e ssential that the power rail recovers quickly at the start of a packet, where the power consumption jumps to high levels. 11.3 low-voltage linear regulator the low-voltage linear regulator is available to power a 1.5v s upply rail. its output is connected internally to vdd_ana, and can be connected externally to the other 1.5v powe r inputs. if the low-voltage linear regulator is used, connect a smoothin g circuit using a low esr 2.2f capacitor and a 2.2 resistor to ground to the output of the low-voltage linear regulator, vdd_ana. alternatively use a 2.2f capacitor with an esr of at least 2?. the low-voltage linear regulator is enabled by either: vregenable_l pin bluetunes rom qfn device firmware bluetunes rom qfn battery charger the low-voltage linear regulator switches into a low power mode when the device is in deep sleep mode, or in reset. when the low-voltage linear regulator is not used, either leave the terminal vregin_l unconnected, or tie it to vdd_ana. 11.4 low-voltage audio linear regulator the low-voltage audio linear regulator is available to power a 1.5v audio supply rail. its output is connected internally to vdd_audio, and can be connected externally to the other 1.5v audio power inputs. if the low-voltage audio linear regulator is used, connect a sm oothing circuit using a low esr 2.2f capacitor and a 2.2 resistor to ground to the output of the low-voltage audi o linear regulator, vdd_audio. alternatively use a 2.2f capacitor with an esr of at least 2?. the low-voltage audio linear regulator is enabled by either: vregenable_l pin bluetunes rom qfn device firmware the low-voltage audio linear regulator switches into a low-powe r mode when no audio cells are enabled, or when the chip is in reset. when this regulator is not used, either leave the terminal vreg in_audio unconnected or tie it to vdd_audio. 11.5 switch-mode regulator csr recommends the on-chip switch-mode regulator to power the 1 .8v supply rail. an external lc filter circuit of a low-resistance series induct or, l1 (22h), followed by a low esr shunt capacitor, c1 (4.7f), is required between the lx terminal and the 1.8v su pply rail. a connection between the 1.8v supply rail and the vdd_smp_core pin is required. a 2.2f decoupling capacitor is required between bat_p and vss. to maintain high-efficiency power conversion and low supply rip ple, it is essential that the series resistance of tracks between the bat_p and vss terminals, the filter and decoupling components, and the external voltage source are minimised. the switch-mode regulator is enabled by either: vregenable_h pin bluetunes rom qfn device firmware bluetunes rom qfn battery charger the switch-mode regulator switches into a low-power pulse skipp ing mode when the device is sent into deep sleep mode, or in reset. when the switch-mode regulator is not required the terminals ba t_p and lx must be grounded or left unconnected. power control and regulation cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 44 of 74 _?q??=olj=nck data sheet free datasheet http:///
11.6 battery charger the battery charger is a constant current / constant voltage ch arger circuit, and is suitable for lithium ion/polymer batteries only. it shares a connection to the battery terminal, bat_p, with the switch-mode regulator. however it may be used in conjunction with either of the high-voltage regulato rs on the device. the constant current level can be varied to allow charging of d ifferent capacity batteries. the charger enters various states of operation as it charges a battery, as listed below. a full operational description is in bluecore5 charger de scription and ca libration proc edure applica tion note : off : entered when charger disconnected. trickle charge: entered when battery is below 2.9v. the battery is charged at a nominal 4.5ma. this mode is for the safe charge of deeply discharged cells. fast charge constant current: entered when battery is above 2.9 v. the charger enters the main fast charge mode. this mode charges the battery at the selected constant cu rrent, i chgset . fast charge constant voltage: entered when battery has reached a selected voltage, v float . the charger switches mode to maintain the cell voltage at the v float voltage by adjusting the charge current. standby: this is the state when the battery is fully charged an d no charging takes place. the battery voltage is continuously monitored and if it drops by more than 150mv be low the v float voltage the charger will re- enter the fast charge constant current mode to keep the battery fully charged. when a voltage is applied to the charger input terminal vdd_chg , and the battery is not fully charged, the charger operates and an led connected to the terminal led[0] illuminate s. by default, until the firmware is running, the led pulses at a low- duty cycle to minimis e current consumption. the battery charger circuitry auto-detects the presence of a po wer source, allowing the firmware to detect, using an internal status bit, when the charger is powered. therefore whe n the charger supply is not connected to vdd_chg, the terminal must be left open-circuit. when not connected, the vdd_chg pin must be allowed to float and not pulled to a power rail. when the battery charger is not enabled this p in may float to a low undefined voltage. any dc connection increases current consumption of the device. capacit ive components may be connected such as diodes, fets and esd protection. the battery charger is designed to operate with a permanently c onnected battery. if the application enables the charger input to be connected while the battery is disconnected , then the bat_p pin voltage may become unstable. this in turn may cause damage to the internal switch-mode regul ator. connecting a 470f capacitor to bat_p limits these oscillations which prevents damage. 11.7 voltage regulator enable pins the voltage regulator enable pins, vregenable_h and vregenable_ l, are used to enable the bluetunes rom qfn device if the on-chip regulators are being us ed. table 11.1 shows the enable pin responsible for each voltage regulator. enable pin regulator vregenable_h switch-mode regulator vregenable_l low-voltage linear regulator and low-voltage audio linear regul ator table 11.1: bluetunes rom qfn voltage regulator enable pins the voltage regulator enable pins are active high, with weak pu ll-downs. bluetunes rom qfn boots-up when the voltage regulator enable pi ns are pulled high, enabling the appropriate regulators. the firmware then latches the regulators on and the voltage regulator enable pins may then be released. the status of the vregenable_h pin is available to firmware thr ough an internal conn ection. vregenable_h also works as an input line. 11.8 reset, rst# bluetunes rom qfn can be reset from several sources: power control and regulation cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 45 of 74 _?q??=olj=nck data sheet free datasheet http:///
rst# pin power-on reset uart break character software configured watchdog timer the rst# pin is an active low reset and is internally filtered using the internal low frequency clock oscillator. a reset is performed between 1.5 and 4.0ms following rst# being active. csr recommends that rst# be applied for a period greater than 5ms. the power-on reset typically occurs when the vdd_core supply fa lls below 1.25v and is released when vdd_core rises above typically 1.30v. at reset the digital i/o pins are set to inputs for bidirectional pins and outputs are tristate. following a reset, bluetunes rom qfn assumes the maximum xtal_in frequ ency, which ensures that the internal clocks run at a safe (low) frequency until bl uetunes rom qfn is configured for the actual xtal_in frequency. if no clock is present at xtal_in, the oscillator in bluetunes rom qfn free runs, again at a safe frequency. 11.8.1 digital pin states on reset table 11.2 shows the p in states of bluetunes rom qfn on reset. pin name / group i/o type no core voltage reset full chip reset uart_rx digital input with pd pd pd uart_cts digital input with pd pd pd uart_tx digital bidirectional with pu pu pu uart_rts digital bidirectional with pu pu pu spi_mosi digital input with pd pd pd spi_clk digital input with pd pd pd spi_cs# digital input with pu pu pu spi_miso digital tristate output with pd pd pd rst# digital input with pu pu pu test_en digital input with pd pd pd pio[14:11,9:0] digital bidirectional with pu/ pd pd pd table 11.2: bluetunes rom qfn digital pin states on reset note: pu = pull-up pd = pull-down pull-up and pull-down default to weak values unless specified o therwise 11.8.2 status after reset the chip status after a reset is as follows: warm reset: data rate and ram data remain available cold reset: data rate and ram data not available 11.9 led drivers bluetunes rom qfn includes 2 pads dedicated to driving led indi cators. both terminals can be controlled by firmware, while led[0] can also be set by the battery charger. power control and regulation cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 46 of 74 _?q??=olj=nck data sheet free datasheet http:///
the terminals are open-drain outputs, so the led must be connec ted from a positive supply rail to the pad in series with a current limiting resistor. csr recommends that the led pad, led[0] or led[1] pins, operate with a pad voltage below 0.5v. in this case, the pad is like a resistor, r on . the resistance together with the external series resistor set s the current, i led , in the led. the current is also dependent on the external voltage, vdd , as figure 11.2 shows. g-tw-0000255.3.2 led forward voltage, v f pad voltage, v pad ; r on = 20 r led led[0] or led[1] resistor voltage drop, v r vdd i led figure 11.2: led equivalent circuit from figure 11.2 it is possible to derive equation 11.1 to calc ulate i led . if a known value of current is required through the led to give a specific luminous intensity, then the value o f r led can be calculated. i led = vdd ? v f r led +r on equation 11.1: led current for the led[0] or led[1] pad to act as resistance, the external series resistor, r led , needs to be such that the voltage drop a cross it, v r , keeps v pad below 0.5v. equation 11.2 also applies. vdd = v f +v r +v pad equation 11.2: led pad voltage note: the led current adds to the overall current, so conservative se lection of the leds will extend battery life. power control and regulation cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 47 of 74 _?q??=olj=nck data sheet free datasheet http:///
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vqrqglvforvxuhdjuhhphqw k&dpeulgjh6lolfrq5dglr/lplwhg 3djhri _?q??=olj=nck 'dwd6khhw free datasheet http:///
13 electrical characteristics 13.1 absolute maximum ratings rating min max unit storage temperature -40 105 c core supply voltage vdd_ana, vdd_l o, vdd_radio, vdd_audio and vdd_core -0.4 1.65 v i/o voltage vdd_pio, vdd_pads and vdd_uart -0.4 3.6 v supply voltage vregin_l -0.4 2.7 v vregin_audio -0.4 2.7 v vregenable_h and vregenable_l -0.4 4.9 v bat_p -0.4 4.4 v led[1:0] -0.4 4.4 v vdd_chg -0.4 6.5 v other terminal voltages vss - 0.4 vdd + 0.4 v 13.2 recommended op erating conditions operating condition min typ max unit operating temperature range -20 20 70 c core supply voltage vdd_ana, vdd_lo, vdd_radio, vdd_audio and vdd_core 1.42 1.50 1.57 v i/o supply voltage vdd_pio, vdd_pads and vdd_uart 1.7 3.3 3.6 v note: for radio performance over temperature refer to bluetunes rom qfn performance specification . bluetunes rom qfn operates up to the maximum supply voltage giv en in the absolute maximum ratings, but rf performance is not guaranteed above 4.2v. electrical characteristics cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 49 of 74 _?q??=olj=nck data sheet free datasheet http:///
13.3 input/output term inal characteristics note: for all i/o termin al characteristics: vdd_ana, vdd_lo, vdd_radio, vdd_audio and vdd_core at 1.50v unl ess shown otherwise. vdd_pio, vdd_pads and vdd_uart at 3.3v unless shown otherwise. current drawn into a pin is defined as positive; current suppli ed out of a pin is defined as negative. 13.3.1 low-voltage linear regulator normal operation min typ max unit input voltage 1.70 1.80 1.95 v output voltage (i load = 70ma / vregin_l = 1.7v) 1.42 1.50 1.57 v temperature coefficient -300 0 300 ppm/c output noise (a) (b) - - 1 mv rms load regulation (100a < i load < 90ma ), v out - - 5 mv load regulation (100a < i load < 115ma ), v out - - 25 mv settling time (a) (c) - - 50 s output current - - 115 ma minimum load current 5 - 100 a quiescent current (excluding load, i load < 1ma) 50 90 150 a low-power mode (d) quiescent current (excluding load, i load < 100a) 5 8 15 a (a) regulator output connected to 47nf pure and 4.7f 2.2 esr capa citors (b) frequency range 100hz to 100khz (c) 1ma to 115ma pulsed load (d) the regulator is in low power m ode when the chip is in deep sle ep mode, or in reset electrical characteristics cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 50 of 74 _?q??=olj=nck data sheet free datasheet http:///
13.3.2 low-voltage linear audio regulator normal operation min typ max unit input voltage 1.70 1.80 1.95 v output voltage (i load = 70ma / vregin_audio = 1.7v) 1.42 1.50 1.57 v temperature coefficient -300 0 300 ppm/c output noise (a) (b) - - 1 mv rms load regulation (100a < i load < 70ma ), v out - - 5 mv settling time (a) (c) - - 50 s output current - - 70 ma minimum load current 5 - 100 a quiescent current (excluding load, i load < 1ma) 25 30 50 a low-power mode (d) quiescent current (excluding load, i load < 100a) 5 8 15 a (a) regulator output connected to 47nf pure and 4.7f 2.2 esr capa citors (b) frequency range 100hz to 100khz (c) 1ma to 70ma pulsed load (d) the regulator is in low power m ode when the chip is in deep sle ep mode, or in reset electrical characteristics cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 51 of 74 _?q??=olj=nck data sheet free datasheet http:///
13.3.3 switch-mode regulator switch-mode regulator min typ max unit input voltage 2.5 - 4.4 v output voltage (i load = 70ma) 1.70 1.80 1.90 v temperature coefficient -250 - 250 ppm/c normal operation output ripple - - 10 mv rms transient settling time (a) - - 50 s maximum load current 200 - - ma conversion efficiency (i load = 70ma) - 90 - % switching frequency (b) - 1.333 - mhz start-up current limit (c) 30 50 80 ma low-power mode (d) output ripple - - 1 mv rms transient settling time (e) - - 700 s maximum load current 5 - - ma minimum load current 1 - - a conversion efficiency (i load = 1ma ) - 80 - % switching frequency (f) 50 - 150 khz (a) for step changes in load of 30 to 80ma and 80 to 30ma (b) locked to crystal frequency (c) current is limited on start-up to prevent excessive stored ener gy in the filter inductor (d) the regulator is in low power m ode when the chip is in deep sle ep mode, or in reset (e) 100a to 1ma pulsed load (f) defines minimum period between pu lses. pulses are skipped at lo w current loads note: the external inductor used with the switch-mode regulator must have an esr in the range 0.3 to 0.7: low esr < 0.3 causes instability. high esr > 0.7 derates the maximum current. electrical characteristics cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 52 of 74 _?q??=olj=nck data sheet free datasheet http:///
13.3.4 battery charger battery charger min typ max unit input voltage 4.5 - 6.5 v charging mode (bat_p rising to 4.2v) min typ max unit supply current (a) - 4.5 6 ma battery trickle charge current (b) - 4 - ma maximum battery fast charge current (i-ctrl = 15) (c) (d) headroom (e) > 0.7v 140 - - ma ma headroom = 0.3v - 120 - minimum battery fast charge current (i-ctrl = 0) (c) (d) ma headroom > 0.7v - 40 - ma headroom = 0.3v - 35 - fast charge step size (i-ctrl = 0 to 15) spread 17% - 6.3 - ma trickle charge voltage threshold - 2.9 - v float voltage (with correct trim value set), v float (f) 4.17 4.2 4.23 v float voltage trim step size (f) - 50 - mv battery charge termination current, % of fast charge current 5 10 20 % (a) current into vdd_chg does not inc lude current delivered to batt ery (i vdd_chg - i bat_p ) (b) bat_p < trickle charge voltage threshold (c) charge current can be set in 16 equally spaced steps (d) trickle charge threshold < bat_p < float voltage (e) where headroom = vdd_chg - bat_p (f) float voltage can be adjusted in 1 5 steps. trim setting is dete rmined in production test and m ust be loaded into the battery c harger by firmware during boot-up sequence standby mode (bat_p falling from 4.2v) min typ max unit supply current (a) - 1.5 2 ma battery current - -5 - a battery recharge hysteresis (b) 100 - 200 mv (a) current into vdd_chg; does not i nclude current delivered to bat tery (i vdd_chg - i bat_p ) (b) hysteresis of (v float - bat_p) for charging to restart electrical characteristics cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 53 of 74 _?q??=olj=nck data sheet free datasheet http:///
shutdown mode (vdd_chg too low or disabled by firmware) min typ max unit supply current - 1.5 2 ma battery current -1 - 0 a vdd_chg under-voltage threshold vdd_chg rising - 3.90 - v vdd_chg falling - 3.70 - v vdd_chg - bat_p lockout threshold vdd_chg rising - 0.22 - v vdd_chg falling - 0.17 - v 13.3.5 reset power-on reset min typ max unit vdd_core falling threshold 1.13 1.25 1.30 v vdd_core rising threshold 1.20 1.30 1.35 v hysteresis 0.05 0.10 0.15 v 13.3.6 regulator enable switching threshold min typ max unit vregenable_h rising threshold 0.50 - 0.95 v falling threshold 0.35 - 0.80 v hysteresis 0.14 - 0.28 v vregenable_l rising threshold 0.50 - 0.95 v falling threshold 0.35 - 0.80 v hysteresis 0.14 - 0.28 v electrical characteristics cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 54 of 74 _?q??=olj=nck data sheet free datasheet http:///
13.3.7 digital terminals supply voltage levels min typ max unit vdd pre 1.4 pre-driver supply voltage 1.5 1.6 v vdd i/o supply voltage (post-driver) 3.0 full spec. 3.3 3.6 v 1.7 reduced spec. - 3.0 v input voltage levels min typ max unit v il input logic level low -0.3 - 0.25 x vdd v v ih input logic level high 0.625 x vdd - vdd + 0.3 v v schmitt schmitt voltage 0.25 x vdd - 0.625 x vdd v output voltage levels min typ max unit v ol output logic level low, l ol = 4.0ma 0 - 0.125 v v oh output logic level high, l oh = -4.0ma 0.75 x vdd - vdd v input and tristate currents min typ max unit i i input leakage current at v in = vdd or 0v -100 0 100 na i oz tristate output leakage current at v o = vdd or 0v -100 0 100 na with strong pull-up -100 -40 -10 a with strong pull-down 10 40 100 a with weak pull-up -5 -1.0 -0.2 a with weak pull-down -0.2 1.0 5.0 a c i input capacitance 1.0 - 5.0 pf resistive strength min typ max unit r puw weak pull-up strength at vdd - 0.2v 0.5 - 2 m r pdw weak pull-down strength at 0.2v 0.5 - 2 m r pus strong pull-up strength at vdd - 0.2v 10 - 50 k r pds strong pull-down strength at 0.2v 10 - 50 k electrical characteristics cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 55 of 74 _?q??=olj=nck data sheet free datasheet http:///
13.3.8 clocks clock source min typ max unit crystal oscillator crystal frequency (a) 16 26 26 mhz digital trim range (b) 5.0 6.2 8.0 pf trim step size (b) - 0.1 - pf transconductance 2.0 - - ms negative resistance (c) 870 1500 2400 external clock input frequency (d) 12 26 52 mhz clock input level (e) 0.4 - vdd_ana v pk-pk edge jitter (allowable jitter), at zero crossing - - 15 ps rms xtal_in input impedance - 10 - k xtal_in input capacitance - 4 - pf (a) integer multiple of 250khz (b) the difference between the internal capacitance at minimum and maximum settings of the internal digital trim (c) xtal frequency = 16mhz; xtal c 0 = 0.75pf; xtal load capacitance = 8.5pf (d) clock input can be any f requency between 12mhz to 52mhz in step s of 250khz plus cdma/ 3g tcxo frequencies of 14.40, 15.36, 16.2 , 16.8, 19.2, 19.44, 19.68, 19.8 and 38.4mhz (e) clock input can be eith er sinusoidal or squ are wave. if the pea ks of the signal are below vss or above vdd_ana a dc blocking c apacitor is required between the signal and xtal_in 13.3.9 led driver pads led driver pads min typ max unit off current - 1 2 a on resistance v pad < 0.5v - 20 33 on resistance, pad enabled by battery charger v pad < 0.5v - 20 50 electrical characteristics cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 56 of 74 _?q??=olj=nck data sheet free datasheet http:///
13.3.10 mono codec: analogue to digital converter analogue to digital converter parameter conditions min typ max unit resolution - - - 16 bits input sample rate, f sample - - 8 - khz signal to noise ratio, snr f in = 1khz b/w = 20hz20khz a-weighted thd+n < 1% 150mv pk-pk input f sample - 8khz 79 - db digital gain digital gain resolution = 1/32 db -24 - 21.5 analogue gain analogue gain resolution = 3db db - - 42 input full scale at maximum gain (differential) - 4 - mv rms input full scale at minimum gain (differential) mv rms - 800 - 3db bandwidth khz - 20 - microphone mode input impedance k - 6.0 - thd+n (microphone input) @ 30mv rms input % - 0.04 - electrical characteristics cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 57 of 74 _?q??=olj=nck data sheet free datasheet http:///
13.3.11 stereo codec: digital to analogue converter digital to analogue converter parameter conditions min typ max unit resolution - - - 16 bits output sample rate, f sample - 8 - 48 khz signal to noise ratio, snr f in = 1khz b/w = 20hz20khz a-weighted thd+n < 0.01% 0dbfs signal load = 100k f sample 8khz - 95 - db 11.025khz - 95 - db 16khz - 95 - db 22.050khz - 95 - db 32khz - 95 - db 44.1khz - 95 - db 48khz - 95 - db digital gain digital gain resolution = 1/32db -24 - 21.5 db analogue gain analogue gain resolution = 3db 0 - -21 db output voltage full-scale swing (differential) (a) - 750 - mv rms allowed load resistive - 16 o.c. capacitive - - 500 pf thd+n 100k load - - 0.01 % thd+n 16 load - - 0.1 % snr (load = 16, 0dbfs input relative to digital silence) - 95 - db (a) any combination of gain (digital and / or analogue) and input s ignal which results in the output signal level exceeding the mi nimum or maximum signal level (analogue or digital ) could result in distortion. electrical characteristics cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 58 of 74 _?q??=olj=nck data sheet free datasheet http:///
13.3.12 auxiliary adc auxiliary adc min typ max unit resolution - - 10 bits input voltage range (a) 0 - vdd_ana v accuracy (guaranteed monotonic) inl -1 - 1 lsb dnl 0 - 1 lsb offset -1 - 1 lsb gain error -0.8 - 0.8 % input bandwidth - 100 - khz conversion time - 2.5 - s sample rate (b) - - 700 samples/ s (a) lsb size = vdd_ana/1023 (b) the auxiliary adc is accessed thro ugh a vm function. the sample rate given is achieved as part of this function. 13.4 esd precautions bluetunes rom qfn is classified as a jesd22-a114 class 2 produc t. apply esd static handling precautions during manufacturing. electrical characteristics cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 59 of 74 _?q??=olj=nck data sheet free datasheet http:///
14 hci power consumption dut role connection packet type description average current unit low-voltage linear regulator switch- mode regulator n/a deep sleep - host connection 0.07 0.07 ma n/a page scan - 1280ms interval 0.48 0.28 ma n/a inquiry and page scan - inquiry (1280ms interval) page (1280ms interval) 0.85 0.49 ma master acl dh1 no traffic 4.3 2.8 ma master acl dh1 file transfer, tx 9.2 5.3 ma master acl dh1 sniff mode (40ms interval, 1 attempt) 2.2 1.4 ma master acl dh1 sniff mode (1280ms interval, 8 attempts) 0.20 0.14 ma master sco hv1 - 39.8 22.3 ma master sco hv3 - 22.2 12.4 ma master sco hv3 sniff mode (30ms interval, 1 attempt) 21.7 12.2 ma master esco ev3 - 22.3 12.4 ma master esco ev5 - 16.3 8.9 ma master esco ev3 setting s1 23.7 13.3 ma master esco 2ev3 setting s2 22.8 12.6 ma master esco 2ev3 setting s3 16.7 9.3 ma master esco 2ev3 setting s3 with sniff mode (100ms interval, 1 attempt) 15.7 8.7 ma slave acl dh1 no traffic 15.2 8.5 ma slave acl dh1 file transfer, rx 17.2 9.3 ma slave acl dh1 sniff mode (40ms interval, 1 attempt) 1.9 1.2 ma slave acl dh1 sniff mode (1280ms interval, 8 attempts) 0.25 0.17 ma slave sco hv1 - 39.9 22.3 ma slave sco hv3 - 27.3 14.8 ma hci power consumption cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 60 of 74 _?q??=olj=nck data sheet free datasheet http:///
dut role connection packet type description average current unit low-voltage linear regulator switch- mode regulator slave sco hv3 sniff mode (30ms interval, 1 attempt) 22.0 12.0 ma slave esco ev3 - 25.3 13.8 ma slave esco ev5 - 21.8 12.0 ma slave esco ev3 setting s1 26.7 14.9 ma slave esco 2ev3 setting s2 26.8 15.0 ma slave esco 2ev3 setting s3 23.9 13.3 ma slave esco 2ev3 setting s3 with sniff mode (100ms interval, 1 attempt) 16.5 9.2 ma note: current consumption values are taken with: vregin_l for low-voltage linear regulator = 1.8v bat_p for switch-mode regulator = 3.7v clock frequency = 16mhz uart baud rate is 115200 qfn device hci power consumption cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 61 of 74 _?q??=olj=nck data sheet free datasheet http:///
15 csr green semiconductor p roducts and rohs compliance 15.1 rohs statement bluetunes rom qfn where explicitly stated in this data sheet me ets the requirements of directive 2002/95/ec of the european parliament and of the council on the restriction of hazardous substance (rohs). 15.1.1 list of restricted materials bluetunes rom qfn is compliant with rohs in relation to the fol lowing substances: cadmium lead mercury hexavalent chromium polybrominated biphenyl polybrominated diphenyl ether in addition, the following substances are not intentionally add ed to bluetunes rom qfn devices: halogenated flame retardant antimony (sb) and compounds, including antimony trioxide flame retardant polybrominated diphenyl and biphenyl oxides tetrabromobisphenol-a bis (2,3-dibromopropylether) asbestos or asbestos compounds azo compounds organic tin compounds mirex polychlorinated napthelenes polychlorinated terphenyls polychlorinated biphenyls polychlorinated/short chain chlorinated paraffins polyvinyl chloride ( pvc) and pvc blends formaldehyde arsenic and compounds (except as a semiconductor dopant) beryllium and its compounds ethylene glycol monomethyl ether or its acetate ethylene glycol monoethyl ether or its acetate halogenated dioxins and furans persistent organic pollutants (pop), including perfluorooctane sulphonates red phosphorous ozone depleting chemicals (class i and ii): chlorofluorocarbons (cfc) and halons radioactive substances for further inform ation, see csr's environmental compliance statement for csr green semiconductor products. csr green semiconductor products and rohs compliance cs-122312-dsp3 production information this material is subject to c sr's non-discl osure agreement ? cambridge silicon radio limited 2008-2009 page 62 of 74 _?q??=olj=nck data sheet free datasheet http:///
16 bluetunes rom qfn software stack bluetunes rom qfn is supplied with bluetooth v2.1 + edr specifi cation compliant stack firmware, which runs on the internal risc mcu. the bluetunes rom qfn software architecture allows bluetooth pr ocessing and the application program to be shared in different ways between the internal risc mcu and an e xternal host processor, if any. the upper layers of the bluetooth stack, above the hci, can be run either on-chi p or on the host processor. 16.1 stand-alone bluetunes rom qfn and kalimba dsp applications hci lm lc program memory 48kb ram bluetooth stack mcu host i/o radio digital audio analogue audio 2 microphones rfcomm sdp stereo headset application internal mcu stereo headset application kalimba dsp dsp control dm1 dm2 pm 2 speaker figure 16.1: stand-alone application: bluetunes rom stereo head set solution note: program memory in figure 16.1 is internal rom. figure 16.1 shows how the bluetunes rom stereo headset solution is built on to the bluetunes rom qfn stack. the application requires no host processor, although it can use a host processor for debugging. all software layers, including the bluetunes rom stereo headset solution software, r fcomm, hci stack etc . run internally. section 16.2 describes the core functionality of the hci stack available on the bluetunes rom qfn. section 16.3 describes the development tools for the bluetunes rom stereo headset solution. section 16.4 describes the features of the bluetunes rom stereo headset solution software. some of these features are run as dsp application code in the dsp program memory ram, e.g. cvc algorithm. this code executes alongside the main bluetunes rom qfn firmware. bluetunes rom qfn software stack cs-122312-dsp3 production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2008-2009 page 63 of 74 _?q??=olj=nck data sheet free datasheet http:///
16.2 hci stack hci lm lc program memory 48kb ram bluetooth stack mcu host i/o radio digital audio host analogue audio 2 microphone uart 2 speaker figure 16.2: bluecore hci stack note: program memory in figure 16.2 is internal rom. in the implementation shown in figure 16.2 the internal process or runs the bluetooth stack up to the hci. the hci stack is part of the overall application stack shown in figure 16.1. 16.2.1 key features of the hci stack: standard bluetooth functio nality csr supports the following bluetooth v2.1 + edr specification f unctionality: secure simple pairing sniff subrating encryption pause resume packet boundary flags encryption extended inquiry response as well as the following mandatory functions of bluetooth v2.0 + edr specification: afh, including classifier faster connection: enhanced inquiry scan (immediate fhs respons e) lmp improvements parameter ranges and optional bluetooth v2.0 + edr specification functionality: afh as master and automatic channel classification fast connect: interlaced inquiry and page scan plus rssi during inquiry esco, ev3 + crc, ev4, ev5 sco handle synchronisation the firmware was written against the bluetooth v2.1 + edr speci fication: bluetooth components: bluetunes rom qfn software stack cs-122312-dsp3 production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2008-2009 page 64 of 74 _?q??=olj=nck data sheet free datasheet http:///
baseband including lc lm hci standard uart hci transport layers all standard bluetooth radio packet types full bluetooth data rate, enhanced data rates of 2 and 3mbps operation with up to 7 active slaves (this is the maximum bluet ooth v2.1 + edr specification allows) scatternet v2.5 operation maximum number of simultaneous active acl connections: 7 maximum number of simultaneous active sco connections: 3 (bluet unes rom qfn supports all combinations of active acl and sco channels for both master and slave operation, as specified by the bluetooth v2.1 + edr specification) operation with up to 3 sco links, routed to one or more slaves all standard sco voice coding, plus transparent sco standard operating modes: page, inquiry, page-scan and inquiry- scan all standard pairing, authentication, link key and encryption o perations standard bluetooth power saving mechanisms: hold, sniff and par k modes, including forced hold dynamic control of peers' transmit power via lmp master/slave switch broadcast channel quality driven data rate all standard bluetooth test modes bluetunes rom qfn software stack cs-122312-dsp3 production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2008-2009 page 65 of 74 _?q??=olj=nck data sheet free datasheet http:///
16.2.2 key features of the hci stack: extra functionality the firmware extends the standard bluetooth functionality with the following features: supports bcsp, a proprietary, reliable alternative to the stand ard bluetooth uart host transport supports h4ds, a proprietary alternative to the standard blueto oth uart host transport, supporting deep sleep for low-power applications provides a set of approximately 50 manufacturer-specific hci ex tension commands. this command set, called bccmd , provides: access to bluetunes rom qfn general-purpose pio port the negotiated effective encryption key length on established b luetooth links access to the firmware random number generator controls to set the default and maximum transmit powers; these can help minimise interference between overlapping, fixed-location piconets dynamic uart configuration bluetooth radio transmitter enabl e/disable. a simple command co nnects to a dedicated hardware switch that determines whether the radio can transmit. a block of bccmd commands provides access to the bluetunes rom qfn persistent store configuration database . the database sets the bluetunes rom qfn bluetooth ad dress, class of device, bluetooth radio (transmit class) configuration, sco routing, lm, etc. a uart break condition is used in 3 ways: presenting a uart break condition to the chip forcing the chip to perform a hardware reboot presenting a break condition at boot time holding the chip in a low power state, preventing normal initialisation while the condition exists with bcsp, sends a break to the host before sending data, when the firmware can be configured. (this is normally used to wake the host from a deep sleep state.) a block of bluetooth radio test or bist commands allows direct control of the bluetunes rom qfn radio. this aids the development of modules' radio designs, and can be used to support bluetooth qualification. hardware low power modes: shallow sleep and deep sleep. the chi p drops into modes that significantly reduce power consumption when the software goes idle. sco channels are normally routed via hci (over bcsp). note: always refer to the firmware release note for the specific func tionality of a particular build. 16.3 bluetunes rom stereo headset solution development kit, btn- 003-1a csrs bluetunes rom stereo headset solution development kit for bluetunes rom qfn, order code btn-003-1a, includes a headset demonstrator board, form-factor representati ve example design, audio adapter, music and voice dongle and necessary interface adapters and cables. in conjunct ion with the bluetunes configurator tool and other supporting utilities the development kit provides the best envi ronment for designing a stereo headset solution with bluetunes rom qfn. 16.4 bluetunes rom qfn stereo hea dset rom softwar e, bc57f687a05 bluetunes rom qfn integrates a stereo audio codec and powerful dsp that enabl es sbc and mp3 decode, and a configurable 5-band eq the headset supports a2dp1.2 and avrcp1.0 profiles enabled with sbc encoder for streaming audio over bluetooth and for remote control functionality the headset supports mp3 decoder for improved audio quality and 5-band eq audio for better user experience the headset supports hfp1.5 and hsp1.0. advanced features in th ese specifications are supported, including 3-way calling. bluetooth v2.1 + edr specification is supported in the rom soft ware including secure simple pairing, greatly simplifying the pairing process. bluetunes rom qfn includes as standard cvc dual and single micr ophone algorithms for echo and noise suppression. cvc dual-microphone algorithm can provide >30db of noise suppre ssion in both stationary and dynamic noise conditions such as; babble, road, music and competing voi ces. in addition an acoustic echo canceller is now integrated into the cvc dual-microphone solution, furthe r enhancing the far-end user experience. a licence key, provided as standard, is required to enable the dual-microphone algorithm. bluetunes rom qfn software stack cs-122312-dsp3 production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2008-2009 page 66 of 74 _?q??=olj=nck data sheet free datasheet http:///
a cvc single-microphone algorithm n provides full-duplex echo ca ncellation and a 10db stationary noise suppressor. the cvc algorithm's are configured for different headset plasti cs using the universal parameter manager tool. for more information see www.csrsupport.com/cvc configure most headset features on the bluetunes rom qfn using the bluetunes configurator tool available from www.csrsupport.com/stereoheadsetsolutions . the tool can be used to read and write headset configurations directl y to the eeprom or alternatively to a psr file. configurable headset features include: bluetooth v2.1 + edr specification features reconnection policies, e.g. reconnect on power on audio features, including default volumes 5-band eq audio enhancements button events: configuring button presses and durations for cer tain events, e.g. double press on pio[1] for last number redial led indications for states, e.g. headset connected, and events, such as power on indication tones for events and ringtones battery divider ratios and thresholds, e.g. thresholds for batt ery low indication, full battery etc. the headset includes the faststream, csrs low latency codec wh ich reduces the latency of the audio link (from source to sink) significantly to avoid lip-sync issu es when listening to audio and watching video images at the same time. the rom software has undergone extensive interoperability testi ng to ensure that it will work with the majority of phones on the market note: access to www.csrsupport.com/cvc and www.csrsupport.com/stereoheadsetsolutions require appropriate access privileges. for more information contact a csr represent ative, email sales@csr.com or go to www.csr.com/contacts . bluetunes rom qfn software stack cs-122312-dsp3 production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2008-2009 page 67 of 74 _?q??=olj=nck data sheet free datasheet http:///
17 ordering information device package order number type size shipment method bluetunes rom qfn cvc 1-mic qfn 68-lead (pb free) 8 x 8 x 0.9mm, 0.4mm pitch tape and reel bc57f687a05-iqf-e4 bluetunes rom qfn cvc 2-mic qfn 68-lead (pb free) 8 x 8 x 0.9mm, 0.4mm pitch tape and reel bs-bc5a05iqf-cvc-2mr3 note: mp3 decode functionality requires an appropriate licence from t homson, see section 17.1. bluetunes rom qfn is a rom-based device where the product code has the form bc57f687axx. xx is the specific rom-variant, 05 is the r om-variant for bluetunes rom s tereo headset solution. minimum order quantity is 2kpcs taped and reeled. to contact a csr representative, email sales@csr.com or go to www.csr.com/contacts 17.1 mp3 licence statement supply of the bluetunes rom qfn does not convey a licence under the relevant intellectual property of thomson and/or frauhofer gesellschaft nor imply any right to use this p roduct in any finished end user or ready-to-use final product. an independent licence for such use is required. for d etails, please visit http://www.mp3licensing.com . 17.2 development kit o rdering information description order number bluetunes rom stereo headset solution development kit, includin g headset example design btn-003-1a ordering information cs-122312-dsp3 production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2008-2009 page 68 of 74 _?q??=olj=nck data sheet free datasheet http:///
18 tape and reel information for tape and reel packing and labelling see ic packing and labelling specification . 18.1 tape orientation figure 18.1 shows the bluetunes rom qfn packing tape orientatio n. g-tw-0002812.2.2 user direction of feed pin 1 figure 18.1: bluetunes rom qfn tape orientation 18.2 tape dimensions g-tw-0002811.3.2 4.0 see note 1 12.0 0.25 r0.25 bo ao ko 1.75 2.0 see note 6 0.30 0.05 a a section a-a 7.5 see note 6 r0.3 max tape and reel information cs-122312-dsp3 production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2008-2009 page 69 of 74 _?q??=olj=nck data sheet free datasheet http:///
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19 document references document reference, date bluecore5 charger description and calibration procedure application note cs-113282-anp, 2007 bluecore5-multimedia external recommendations for esd protection cs-114058-anp, 2007 bluetooth and ieee 802.11 b/g co-existence solutions overview bcore-an-066p, 2005 bluetunes rom qfn performance specification cs-122327-spp, 2009 core specification of the bluetooth system v2.1 + edr, 2007 ic packing and labelling specification cs-112584-spp, 2007 moisture / reflow sensiti vity classification for nonhermitic solid state surface mount devices ipc / jedec j-std-020 optimising bluecore5-multimedia adc performance application note cs-120059-an, 2008 selection of i 2 c eeproms for use with bluecore bcore-an-008p, 2003 test suite structure (tss) and test purposes (tp) system specification 1.2/2.0/2.0 + edr/ 2.1/2.1 + edr rf.ts/2.1.e.0, 2006 typical solder reflow prof ile for lead-f ree devices cs-116434-anp, 2007 document references cs-122312-dsp3 production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2008-2009 page 71 of 74 _?q??=olj=nck data sheet free datasheet http:///
terms and definitions term definition 8dpsk 8-phase differential phase shift keying /4 dqpsk /4 rotated differential quaternary phase shift keying -law audio companding standard (g.711) a-law audio companding standard (g.711) a2dp advanced audio distribution profile ac alternating current acl asynchronous connection-oriented adc analogue to digital converter adpcm adaptive differential pulse code modulation (e.g g.726) afh adaptive freque ncy hopping agc automatic gain control aio analogue input/output alu arithmetic logic unit auristream csr proprietary adpcm codec avrcp audio/video remote control profile bccmd bluecore command bcsp bluecore serial protocol bist built-in self-test bluecore ? group term for csrs range of bluetooth wireless technology ics bluetooth ? set of technologies providing audio and data transfer over shor t-range radio connections bmc burst mode controller bom bill of materials cfc chlorofluorocarbon codec coder decoder crc cyclic redundancy check csr cambridge silicon radio cts clear to send cvc clear voice capture cvsd continuous variable slope delta modulation dac digital to analogue converter dc direct current dnl differential non linearity (adc accuracy parameter) dsp digital signal processor dut device under test e.g. exempli gratia , for example edr enhanced data rate eeprom electrically erasable programmable read only memory eq equaliser esco extended sco esd electrostatic discharge esr equivalent series resistance terms and definitions cs-122312-dsp3 production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2008-2009 page 72 of 74 _?q??=olj=nck data sheet free datasheet http:///
term definition etc et cetera , and the rest, and so forth fec forward error correction fet field effect transistor fhs frequency hop synchronisation fsk frequency shift keying gfsk gaussian frequency shift keying gsm global system for mobile communications h4ds h4 deep sleep hci host controlle r interface hec header error check correction hfp hands-free profile hsp headset profile i2c inter-integrated circuit interface i/o input/output ic integrated circuit if intermediate frequency iir infinite impulse response (filter) inl integral non linearity (adc accuracy parameter) iq in-phase and quadrature jedec joint electron device engineerin g council (now the jedec solid state technology association) kalimba an open platform dsp co-processor, enabling support of enhanced audio applications, such as echo and noise suppression, and file compression / decompres sion kb kilobyte lc an inductor (l) and capacitor (c) network lc link controller ldo low (voltage) drop-out led light-emitting diode lm link manager lmp link manager protocol lna low noise amplifier lsb least-significant bit (or byte) mac medium access control mac multiplier and accumulator mbps megabits per second mcu microcontroller unit mips million instructions per second miso master in slave out mmu memory management unit mp3 mpeg-1 audio layer 3 n/a not applicable nc not connect nsmd non solder mask defined o.c. open circuit terms and definitions cs-122312-dsp3 production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2008-2009 page 73 of 74 _?q??=olj=nck data sheet free datasheet http:///
term definition pa power amplifier pc personal computer pcb printed circuit board pcm pulse code modulation pio programmable input/output plc public limited company pop persistent organic pollutants ppm parts per million ps key persistent store key psrr power supply rejection ratio pvc poly vinyl chloride qfn quad-flat no-lead ram random access memory rc resistor capacitor rf radio frequency rfcomm radio frequency communication. protocol layer providing serial port emulation over l2cap risc reduced instruction set computer rohs restriction of hazardous substances in electrical and electroni c equipment directive (2002/95/ec) rom read only memory rssi received signal strength indication rts request to send rx receive or receiver sbc sub-band coding sco synchronous connection-oriented sig (bluetooth) special interest group smps switch mode power supply snr signal-to-noise ratio spi serial peripheral interface spl sound pressure level tcxo temperature controlled crystal oscillator thd+n total harmonic distortion and noise tx transmit or transmitter uart universal asynchronous receiver transmitter vco voltage controlled oscillator vm virtual machine w-cdma wideband code division multiple access terms and definitions cs-122312-dsp3 production information this material is subject to c sr's non-disclosure agreement ? cambridge silicon radio limited 2008-2009 page 74 of 74 _?q??=olj=nck data sheet free datasheet http:///

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